Rafath Achugatla

Actively Seeking internships in Digital Design and Verification / Computer Architecture starting immediately.

UVM environment-based verification of Asynchronous FIFO, Designed a synthesizable RTL for asynchronous FIFO and developed a UVM-based testbench. Functional Verification of APB Protocol, Prepared a verification plan to verify the functionality of the APB protocol. Simulation of DDR5 Memory Controller Scheduling Algorithm, Simulated a DDR5 memory controller for a 12-core 4.8 GHz processor. Simulation of Level 1 Split Cache with MESI protocol and LRU, Simulated a Split L1 Cache for a 32-bit processor. Transaction/Bus Functional Modeling of Intel 8088 Bus, Simulated and implemented an interface for the Intel 8088 microprocessor. Design and Verification of leading zero detectors, Arbiter, Designed different leading zero detectors variants and developed exhaustive self-checking testbenches.