Rahil Vahora

Responsibilities & Achievements:

• Led the design and development of electronic systems for Rivian's electric vehicles, integrating hardware and software solutions to enhance system performance and reliability.
• Designed and optimized complex circuits and PCB layouts, meeting rigorous industry standards while achieving a recordable improvement in design efficiency.
• Collaborated on hardware/software co-design projects, aligning hardware development with embedded software requirements to reduce integration issues by 85%.
• Developed FPGA and ASIC solutions for vehicle control systems, utilizing tools like Xilinx Vivado and ModelSim for simulation and validation.
• Conducted RTL design, synthesis, and timing analysis using Synopsys Design Compiler and Cadence Virtuoso, ensuring robust hardware performance and efficient functionality.
• Reduced power consumption in embedded systems by implementing advanced clock-gating techniques, achieving desirable energy savings.
• Spearheaded debugging and validation efforts for hardware/software interactions, improving system robustness and reducing error rates effectively
• Delivered key project milestones ahead of deadlines, contributing to the successful launch of Rivian’s next-generation electric vehicles.
• Streamlined workflows for RTL-to-GDSII design using automated processes, cutting design cycle time.

• Assisted in the physical design and implementation of integrated circuits, focusing on floorplanning, placement, and routing tasks using industry-standard tools.
• Conducted timing analysis (STA) and optimized circuit performance to meet stringent power and area constraints.
• Performed LVS/DRC checks to ensure layout compliance with design rules and verified netlist accuracy using formal verification tools.
• Gained hands-on experience with Cadence Encounter and Synopsys IC Compiler, contributing to successful project deliverables within tight timelines.
• Collaborated with senior engineers to resolve design challenges, improving overall system reliability and functionality.
• Supported parasitic extraction and analyzed its impact on design performance, ensuring design integrity from synthesis to layout.