RAJARSHI MUKHERJEE
Dublin,California
Summary
Results-driven Executive and Technologist with over 20 years of experience in developing and deploying multi-million-dollar EDA products for low power verification, clock domain crossing, LINT and reset domain crossing verification, equivalence checking and formal verification solutions. Spearheaded machine learning innovations in VC LP and VC SpyGlass tools to enhance customer productivity. Expertise in EDA technologies, hardware security, and HAPS workflows, complemented by a strong track record of delivering innovative solutions and over 30 publications and 35 patents.
Overview
29
29
years of professional experience
Work History
Senior Architect
Synopsys
01.2023 - Current
- Led Architectural Design of Complex Flows leveraging Telemetry and ML-based collection and analysis of tool crashes to improve crash fix turnaround times by 5X
- Collaborated with cross-functional teams in HAPS to define and develop ML-based solution for 30% speedup in compilation and defined integration strategies
- Collaborated with cross-functional ZeBu team to develop ML-based early prediction of runtime and memory of key stages to improve customer efficiency by 3X
- Developed Strategic Roadmap for use and deployment of AI Agents for enhanced usability of key Tools in Central Engineering
- This work has led to several publications at Synopsys Innovation Leadership Conference (SILC)
Group Director
Synopsys
01.2021 - 01.2023
- Managed a multi-site R&D Team of 70+ Engineers working on 10+ critical projects
- Led project to get 20% reduction of Functional Bugs in HAPS front-end through collaboration with Formality Team to build a formal verification solution
- Led a critical project on clock propagation to improve accuracy and achieve 2X speedup
- Doubled project execution efficiency by driving functional and design specifications, reviewing test plans, quality metrics, root-cause analysis for customer bugs, progress dashboards for projects and initiatives and scrums
- Led project to support Transactors in HAPS flow, plugging a competitive gap and speeding up deployment at a major customer
- Led support of Xilinx Versal device in HAPS flow leading to 2X capacity and performance driving 20% more customer adoptions
- Managed Partitioning, Clocks, Debug, Synthesis & Mapping, Timing and UI teams and worked closely with Compile, Firmware, System Route, System Generate and P&R teams
Group Director
Synopsys
01.2011 - 01.2021
- Managed a multi-site R&D Team of 85+ Engineers, working on 30+ critical projects
- Built Low Power, CDC, LINT, RDC and Constraints Checking Products on VC SpyGlass platform ground-up with 3X better performance over competition leading to wider customer adoption and 2X growth in revenue
- Drove key technologies, innovation, and decisions on SW Architecture, Algorithms and Flows leading to 3X competitive advantage and 2X performance gains
- Defined technology roadmap for VC LP, SpyGlass & VC SpyGlass CDC, LINT and RDC Products for a 2 years+ horizon
- Led application of ML (unsupervised learning - developed with K-Means, Mean-Shift, Birch and hierarchical clustering with application of PCA) for automated root-cause analysis from LP, CDC and LINT run results for 10X quicker debug by customers and led to customer testimonials and higher adoption rates
- Led integration of teams, technologies and processes after Atrenta acquisition to build best-in-class Signoff Products leading to 3X performance advantage over competition and 2X revenue growth
- Worked closely with AE team on customer engagements and deployments for both SpyGlass and VC SpyGlass product families
- Co-authored solution proposal to win a DARPA grant to develop HW Security Verification products in VC SpyGlass platform
- For DARPA project led development of novel solutions for HW Threat Detection including Cyclomatic Complexity, Data Flow Vulnerability, FSM Vulnerability, Clock and Reset Path Vulnerability along with an actionable composite vulnerability score
- Collaborated with a key SoC customer to develop security solution proposal to replace customer in-house tool and explored CWE vulnerabilities
- Work on SpyGlass and VC SpyGlass technologies led to several co-authored US Patents & Publications
- SpyGlass and VC LP have won the prestigious Synopsys Quality Award
Senior Manager
Synopsys
01.2009 - 01.2011
- Led invention of technology to automatically root-cause Constraints Solver Failures resulting in a US Patent
- Managed team of 6 R&D engineers to deliver 5+ key projects for VCS Constraints, resulting in 20% performance gain and improved quality, enhancing customer satisfaction
- Contributed to software development for key projects including Bounded Constraints, addressing competitive gap in product offerings
Director
Atrenta
01.2007 - 01.2009
- Developed algorithms achieving 1.5X speedup in TXV (Timing Exception Verification flow), enhancing customer deployment and satisfaction
- Developed algorithms that improved QoR of TXG (Timing Exception Generation) flow, driving increased customer adoption
Architect
Calypto
01.2003 - 01.2007
- Developed and deployed the bit-level solver of SLEC by integrating ABC SAT Solver from UC Berkeley leading to solution of 3X additional sub-problems
- Developed and deployed Constraints Engine to automatically apply correct constraints to signal pairs of the two designs being compared leading to higher levels of automation and helped drive customer adoption of SLEC
- Developed and deployed critical engines of SLEC, the first Sequential Logic Equivalence Checker in industry
- This work led to several co-authored US Patents
Member Research Staff
Fujitsu Laboratories
01.1997 - 01.2003
- Developed pioneering industrial solution for automated combinational equivalence checking
- Deployed combinational equivalence checking product at Fujitsu, enhancing product verification capabilities
- Co-authored US patents and publications resulting from this work
Education
PG Program in Artificial Intelligence & Machine Learning - Business Applications
University of Texas at Austin
PG Program on AI Agents -
Great Learning
PhD - Computer Engineering
University of Texas at Austin
MS - Computer Science
Texas A&M University
BS - Electronics and Electrical Communication Engineering
IIT
Skills
- C
- C
- Perl
- TCL
- Python
- Verilog
- VHDL
- Simulation
- Clocks
- Constraints
- Timing
- Synthesis
- Debug
- P&R
- Low Power
- CDC
- RDC
- LINT
- Generative AI
- AI Agents
- RAG
- LangChain
- LangGraph
- Google-ADK
- Supervised ML
- Unsupervised ML
- Pandas
- NumPy
- Scikit-Learn
- Keras
- PyTorch
- HuggingFaceHub
- BDD
- SAT Solvers
- Equivalence Checking
- Model Checking
- AWS
Awards
SpyGlass and VC LP have won the prestigious Synopsys Quality Award
Publications And Patents
35+ co-authored publications in leading conferences and journals, 30+ co-authored patents
Timeline
Senior Architect
Synopsys
01.2023 - Current
Group Director
Synopsys
01.2021 - 01.2023
Group Director
Synopsys
01.2011 - 01.2021
Senior Manager
Synopsys
01.2009 - 01.2011
Director
Atrenta
01.2007 - 01.2009
Architect
Calypto
01.2003 - 01.2007
Member Research Staff
Fujitsu Laboratories
01.1997 - 01.2003
PG Program in Artificial Intelligence & Machine Learning - Business Applications
University of Texas at Austin
PG Program on AI Agents -
Great Learning
PhD - Computer Engineering
University of Texas at Austin
MS - Computer Science
Texas A&M University
BS - Electronics and Electrical Communication Engineering
IIT