Summary
Overview
Work History
Education
Skills
Accomplishments
Timeline
Generic

RAJENDRA KODVALLA

California

Summary

10+ Years of Experience in ASIC Chip/Block level physical design implementation tasks on Multimillion Gate designs from RTL to GDS-II & an individual contributor right from customer interaction to realization including, Design feedback and all sign-off closure tasks.

Overview

11
11
years of professional experience

Work History

Physical Design Engineer

Capgemini
05.2014 - Current

Microsoft

Currituck County Schools
09.2024 - 04.2025
  • Full ownership of the top-level work.
  • Done floorplan with sub IPs, IO pads, signal and power micro bumps, and ESD placement.
  • Full RDL/SRDL routing with proper power planning and understanding, with multiple views such as RV, LV, PV, and ESD.
  • ESD planning with single-layer RDL interconnection for better quality results.
  • RDL routing for HF clock, signal, analog, and digital power bumps with IO pad connections.
  • With architecture awareness, I created an excellent floor plan with analog and digital I/O pads.
  • Completed a successful tape-out in a limited time period.

INTEL

MMG
10.2023 - 09.2024
  • Multiple IP support and one IP ownership with 20 blocks for RV, DRC, and LVS.
  • Responsible for all design congestion issues and fix suggestions for all blocks.
  • Provide more fixed suggestions related to bump planning at the right time.
  • Responsible for all power grid issues and power supply for all the cells.
  • I need to analyze all RV-related static, dynamic, rascal, PG-EM, and SIG-EM violations and fix suggestions.
  • The critical and challenging task is to develop a secondary power grid strategy to supply all LS cells.
  • I created my own power grid from top to bottom to avoid those secondary power grid issues.
  • Voltage area placements are refined with respect to timing, RV, and architecture perspective.

INTEL

DPT8
06.2023 - 09.2023
  • Full ownership of the block.
  • Need to close the timing and RV for the block.
  • Fixed BUMP-related RV issues in the full chip for static and dynamic voltage drop.
  • Fixed IR violations, such as peak, EM, static, and dynamic voltage drop issues on other blocks.
  • Faced static grid issues in this design due to the lower density of the power grid.

INTEL

GT ELASTI
03.2022 - 06.2023
  • Member of the PD team and owner of two designs from synthesis to GDS clean database.
  • Need to meet congestion, timing, RV, power, DRC, and other important criteria.
  • Experimenting with multiple floorplan techniques and logic placement.
  • Major fixes happened for congestion and timing.
  • Two designs are fully congested designs and RP-dominated blocks.
  • Gained multi-voltage domain knowledge with level shifter placement.

INTEL

ICXD
01.2021 - 02.2022
  • Member of the PD team and owns 1 design from synthesis to GDSII clean database.
  • Providing the PnR team with a good QoR netlist that meets timing, density, congestion, and other important criteria.
  • Experimenting on multiple floorplans in DC Topo to come up with an optimum floorplan for PNR.
  • Worked for all sign-off checks.
  • The design was a latch-dominated design, and I learned how to analyze latch-based designs.

INTEL

CI-DIG TOP
03.2020 - 12.2020
  • Member of the PD team and owns 1 design.
  • Need to close the timing and RV for the block.
  • Fixed BUMP-related RV issues in the full chip for static and dynamic voltage drop.
  • Fixed IR violations, such as peak, EM, static, and dynamic voltage drop issues on other blocks.
  • Learned more about RV-related issues and gained full chip bump placement.

ICXD-HCC
03.2019 - 02.2020
  • Team Member and Lead
  • Worked for all project related setup from scratch
  • Need to create all 114 blocks on the dart page
  • Need to do one flow flush for all the partitions
  • Worked for all blocks IR setup on the DART page
  • Guided team members on the Right path for all dart flows and initial project setup
  • The design was a replication of the previous project, but they didn’t open all blocks, due to that I learned more in central runs

ICXD-LCC
01.2018 - 02.2019
  • I need to run all sign-off tools in DART
  • Worked for all PNR flows for 4 blocks
  • Worked for those 4+25 blocks Dart setup and CV runs
  • Worked for all sign-off checks
  • Worked related to Review stuff for all 29 blocks

AMD

KINGSTON
10.2017 - 12.2018
  • Company Overview: AMD.
  • Team Member.
  • Need to support EMIR for all 72 blocks.
  • Worked for static IR, dynamic IR, and signal EM.
  • AMD

INTEL

R-NAC
11.2016 - 09.2017
  • Need to implement netlist to GDSII.
  • Worked for Floorplan, timing, and DRC LVS.

Education

B-Tech - Electronics & Communication

01.2010

Diploma - Electronics & Communication

01.2006

Skills

  • Extensive experience in ASIC physical implementation from RTL to GDS-II
  • Excellent skills in full chip floorplan, bump, GPIO, ESD, analog and digital pad placement, and PG grid
  • Strong experience in top- and block-level RV analysis in static, dynamic, Sig-Em, PG-EM, thermal, and Res-check
  • Chip and block-level experience in physical implementation, floorplan, power plan, power grid creation, placement, CTS, routing, and timing closure
  • Excellent hands-on experience in manual routing from top to bottom, including BUMP planning and RDL routing
  • Experience in multi-power domain designs and complexity with multimillion
  • Experience in DRC, LVS, ERC, ESD, and antenna analysis
  • Worked on different tech nodes like 65 nm, 40 nm, 28 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, and 2 nm, such as Global Foundry, TSMC, and Intel
  • Worked in leading semiconductor industries such as Microsoft, Intel, AMD, and STMicroelectronics
  • Skilled user of Synopsys, Cadence, Mentor, and Apache implementation and signoff tools
  • Worked on different flow methodologies like Cheeta, RDT, Tile Builder, Dart, R2G, and Genesys, etc
  • Experience at the SS level and Block Level Dart/CV runs in 5 to 6 projects

Accomplishments

  • Got Outstanding contribution in Delivery – Team Award (ER&D)
  • Have been recognized under WOW - Individual Excellence Award by Manager for Client First.
  • Got STAR Award for Outstanding performance and lasting contribution (ER&D).

Timeline

Microsoft

Currituck County Schools
09.2024 - 04.2025

INTEL

MMG
10.2023 - 09.2024

INTEL

DPT8
06.2023 - 09.2023

INTEL

GT ELASTI
03.2022 - 06.2023

INTEL

ICXD
01.2021 - 02.2022

INTEL

CI-DIG TOP
03.2020 - 12.2020

ICXD-HCC
03.2019 - 02.2020

ICXD-LCC
01.2018 - 02.2019

AMD

KINGSTON
10.2017 - 12.2018

INTEL

R-NAC
11.2016 - 09.2017

Physical Design Engineer

Capgemini
05.2014 - Current

B-Tech - Electronics & Communication

Diploma - Electronics & Communication

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RAJENDRA KODVALLA