RAM GANESH NALLAMATTI
San Jose
Summary
Diligent College Student focused on VLSI Design and dedication to prompt project completion and continual adaptation. Team-oriented collaborator with reliability and focus on equitable task distribution through group projects and motivation to accomplish mutually held goals.
Overview
2
2
years of professional experience
Work History
Engineer-I ASIC Design
Alphawave SEMI
Bangalore, Karnataka
12.2021 - 07.2023
- Had Experience in Designing ASIC Chip in 7nm,12nm,16nm,28nm Technologies using various EDA Tools.
- Performed physical synthesis, place and route and timing analysis of the designs.
- Analyzed RTL code for functional correctness, timing constraints and power optimization.
- Identified potential risks throughout the entire ASIC design flow and developed mitigation strategies accordingly.
Intern
Open Silicon Research Private Ltd
Bangalore, Karnataka
06.2021 - 11.2021
- Had gone through the Topics on ASIC Physical design Backend (Synthesis and PnR) and Static Timing Analysis.
- Reviewed customer's specification documents thoroughly before starting any task related to ASIC design.
- Assisted senior engineers in troubleshooting any hardware issues related to ASIC designs.
Education
B.Tech - Electronics And Communication Engineering
Sagi Rama Krishnam Raju Engineering College
05.2021
Masters - Computer Engineering
San Jose State University
San Jose, CA 08.2023 - Current
Skills
- Linux,Tcl,Verilog,Cisco Packet Tracer
- Innovus, Timevision,Tempus, Calibre, Voltus,Multisim
- Layout design
- Interpersonal Communication
Projects
- Development of Chip for Super Computers
Physical Designing of a Chip in 16nm Technology which was being used in computers.
Set up the PnR Flow,designed and optimized the design of a sub-block. Timing
Signoff and verified physically using calibre for that block. - Development of chip for Drone level technology
Worked on sub-block of SoC chip of 12nm technology. Designed and optimized the design.
Timing Signoff and verified physically using calibre for that block. - SDC Constraint Analysis using Timevision
Constraint analysis on the SDC file of ASIC chip designing project using timevision tool in different modes such as func, scan, mbist. - Digital Image Watermarking using Modern Techniques
Chaotic Maps, Integer-wavelet Transform are the techniques used and implemented with the help of MATLAB.
PUBLICATIONS
- Published the Paper on ”Generation of Chaotic Watermark Image using SVD and
IWT” at Mukt Shabd Journal ISSN NO:2347-3150.
Work Availability
monday
tuesday
wednesday
thursday
friday
saturday
sunday
morning
afternoon
evening
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Timeline
Masters - Computer Engineering
San Jose State University
08.2023 - Current
Engineer-I ASIC Design
Alphawave SEMI
12.2021 - 07.2023
Intern
Open Silicon Research Private Ltd
06.2021 - 11.2021
B.Tech - Electronics And Communication Engineering
Sagi Rama Krishnam Raju Engineering College
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