Engineer, Architecture
Achronix Semiconductor Corporation
3 2022 - Current
- Performed verification tasks relating to different subsystems like resets, aes cryptographic engine, and BRAM.
- Developed testbenches in system verilog from scratch that instantiates our FPGA, binds port signals, and coverpoints.
- Utilized Synopsys VCS and Verdi/DVE to compile and simulate test designs.
- Analyzed design specs, created coverage plans, and performed coverage closure.
- Worked with design engineers to finalize verification tasks.
- Utilized software programming languages such as Python, TCL, and Makefile to automate testing and test randomization.
- Performed debug with hardware and simulation.
- Performed bring up validation for PCIe subsystem utilizing Lecroy Z516, and custom soft ip designs created with synthesizable rtl logic.
- Created test designs and testcases that would be tested on the FPGA via Hardware-In-Loop (HIL), and also created a script that gathers the results to be outputted in html format with Python.
- Utilized Perforce for version control when checking in changes or adding in new designs.
- Performed automation tasks involving a hardware to software bridge using ssh and python.
