Ravali Pasham
SoC Design Verification Engineer
Hillsboro,OR
Summary
Experienced with verification methodologies, ensuring comprehensive and accurate testing of designs. Utilizes problem-solving skills to identify and resolve issues early in development process. Knowledge of collaborative techniques to work efficiently within diverse teams.
Overview
7
7
years of professional experience
Work History
Senior SoC Design Verification Engineer
INTEL CORPORATION
12.2021 - Current
- Created power management (PM) test plans to validate next-generation Server SoCs through simulation and emulation, determining necessary infrastructure for monitors and checkers in the SoC environment.
- Led team in validating critical PM features such as DVFS, ADR, C-State, and RAPL across multiple generations of Server SoCs using emulation and simulation.
- Played a key role in the verification of low-power design, ensuring accurate validation of power management features and optimizing energy efficiency across various Server SoC generations.
- Developed UVM test sequences and Python checkers for validating key SoC features, ensuring compatibility across multiple projects for emulation-based tests.
- Automated randomized testing for PM cross-traffic flows, enhancing test coverage across different SoC generations.
- Implemented coverage metrics for power management features, improving SoC coverage and ensuring thorough evaluation of system performance and efficiency.
- Collaborated with cross-functional teams to define test requirements and establish the testbench setup for the D2D stack on the latest Intel SoC servers, including the integration of monitors, checkers, and coverage models to ensure thorough validation of the system.
- Played a key role in integrating new tools into the verification methodology, significantly improving efficiency in coverage analysis and checker implementation.
- Debugged and identified RTL and firmware bugs, collaborating with architects to resolve issues.
- Worked closely with the Silicon Lab Engineering (SLE) team to address post-silicon bugs, replicate issues in pre-silicon environments, and improve validation coverage for future iterations.
- Mentored interns and newly joined RCG team members since 2022, providing project guidance, facilitating team integration, and supporting professional development.
SoC Validation Engineer
INTEL CORPORATION
08.2018 - 12.2021
- Accountable for creating and implementing automated regression tests for pre-silicon hardware, specifically targeting the power management features of Intel Server chips. This involved developing test scripts to ensure robust validation of power management functionalities before silicon fabrication.
- Experience on working on emulation and simulation environment for the validation for PM flows ( RAPL,UFS)
- Managed the initiation of extensive validation runs and conducted thorough triaging of failures.This process involved overseeing large-scale test executions, analyzing test results to identify and diagnose issues, and prioritizing them for resolution to ensure system reliability and performance.
- Conducted root cause analysis on deviations during validation activities, enabling timely resolution of technical issues.
- Worked on enabling PM cross Reset flows .
- Worked on enabling scripts for the PM flows to identify successful Reset and PM initial setup.
Education
Master of Science - Electrical and Computer Engineering
Portland State University
9 2016 - 6 2018
Skills
- Programming and scripting Languages : Verilog, SystemVerilog, C, Python, Perl
- Verification & Simulation tools: Mentor Questa, Synopsys VCS, Verdi, Emulation, Simulation
- Methodologies & Techniques: UVM, Functional Coverage, Assertion-based Verification, Coverage-driven Verification, Verification Planning, Constraint Random Testing
- Design & Testing: RTL Design, Testbench Development
- Protocols: Coherency Protocols (MESI, MOESI, MSI), ARM AMBA (AXI, AHB, APB), PCIe, PCIe CXL
Timeline
Senior SoC Design Verification Engineer
INTEL CORPORATION
12.2021 - Current
SoC Validation Engineer
INTEL CORPORATION
08.2018 - 12.2021
Master of Science - Electrical and Computer Engineering
Portland State University
9 2016 - 6 2018
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