RAVI P
Tampa,FL
Summary
Experienced semiconductor professional skilled in RTL design, physical design, and research. Proficient in the entire design flow from RTL coding to GDS II file generation. Strong background in performance verification, layout verification, and timing closure. Demonstrated expertise in mentoring, implementing advanced methodologies, and leveraging machine learning-driven automation for design optimization. Proven track record of delivering high-quality designs across multiple technology nodes and semiconductor projects.
Overview
4
4
years of professional experience
Work History
Research Assistant
University of South Florida
02.2024 - Current
- Involved in the entire design process, from RTL coding to generating final GDS II files for fabrication, showcasing hands-on experience in semiconductor design
- Actively engaged in projects focused on ML-driven automation, utilizing state-of-art techniques to automate various aspects of thedesign process
- Exploring and implementing ML algorithms to enhance efficiency, reduce design cycle times, and optimize different stages of design flow, demonstrating proficiency in machine learning techniques.
Physical Design Intern
SmarTeq Solutions
01.2023 - 08.2023
- Conducted detailed analysis of static and IR drop issues in the Ethernet switch project at Texas Instruments, employing advanced methodologies to ensure optimal performance and reliability under various operating conditions
- Demonstrated leadership by effectively mentoring and guiding two team members in their Physical Design (PNR) activities, fostering a collaborative and productive work environment while accelerating project timelines
- Engineered vertical and horizontal DDR super buffers for Qualcomm projects, meticulously refining power structures and implementing innovative routing strategies to achieve superior performance and power efficiency
- Leveraged Virtuoso tools to extract layout data and initiate the physical design process for analog blocks in gaming chips at Maxim, contributing to the seamless integration of analog functionalities and ensuring design robustness
- Collaborated with cross-functional teams to address post-layout optimization requirements, implementing spare modules and yield improvement techniques to enhance design resilience and manufacturability
- Played a pivotal role in conducting comprehensive post-layout checks, including Logic Equivalence Checking (LEC) and Post-Mask Signoff, to verify design integrity and compliance with industry standards
- Demonstrated proficiency in backend design methodologies, physical verification techniques, and design optimization strategies across diverse semiconductor projects, showcasing a strong track record of delivering high-quality designs on schedule.
Physical Design Engineer
Wipro Limited
01.2020 - 12.2021
- Conducted performance verification tasks, encompassing static timing analysis (STA) and timing convergence activities
- Utilized industry-standard tools to analyze timing paths and ensure that design specifications were met within the specified timing constraints
- Managed clocking strategies within the block, overseeing four clocks with the highest frequency reaching 700MHz
- Coordinated clock distribution to ensure synchronous operation and timing alignment across the design
- Led layout verification efforts, including Design Rule Checks (DRC), Layout versus Schematic (LVS) checks, and implementation of low-power design techniques
- Addressed issues related to layout compliance, power consumption, and functional correctness to ensure design robustness
- Implemented top-level and block-level timing fixes to address timing violations and achieve timing closure objectives
- Conducted IR analysis and implemented fixes to mitigate voltage drop issues and ensure reliable operation under dynamic conditions
- Facilitated interface timing closure, collaborating with cross-functional teams to refine interface timing specifications and ensure seamless integration of block-level designs into the overall system architecture
- Conducted Logic Equivalence Checking (LEC), analyzing unmapped points, aborts, and non-equivalences to verify design accuracy and functional correctness
- Employed corrective measures to resolve discrepancies and maintain design integrity throughout the verification process
- This experience underscores proficiency in performance verification, clock management, layout verification, timing closure, low-power design, and logic equivalence checking, demonstrating a comprehensive skill set in semiconductor design and verification methodologies.
Education
Master of Science - Electrical Engineering
University of South Florida
Tampa, FL12.2023
Bachelor of Technology - Electrical, Electronics Engineering Technologies
Lovely Professional University
Punjab, India06.2020
Skills
- Digital Logic Design
- FPGA Prototyping
- Physical Design
- RTL to GDSII Flow
- Clock Tree Synthesis
- Static Timing Analysis
- Computer Architecture
- Logic & Physical Synthesis
- Layout Design
- Physical Verification (DRC LVS)
- IC Fabrication
- Photolithography procedures
- Ultra Clean Room Environment
- Oxidation
- Diffusion
- Ion Implantation
- Advanced Barrier Materials for Copper Interconnects
- Thin Film Deposition
- Reactive Ion Etching
- Plasma Etching
- Packages
- Cadence Virtuoso
- Calibre
- ADE
- Synopsys Design Compiler NXT
- VCS
- Genus
- Innovus
- Tempus
- Modus
- Xcelium
- Conformal LEC
- ModelSim
- Intel Quartus Prime
- Xilinx ISE
- HSpice
- MATLAB
- MS Office
- Programming languages
- Verilog
- System Verilog
- VHDL
- UVM
- OVM
- Assertions
- Functional Coverage
- Python
- C
Websites
Projects
Design and Synthesis of a Custom ASIC N N Bit Array Multiplier Layout, Cadence Virtuoso - Calibre - HSpice, Orchestrated layout design for a 16x16 Multiplier with CPA and CSA, on 0.5µm technology. Executed Full Custom Design integrating Shift Registers, NAND, NOR gates, and a Full Adder with AND Gate. Generated Netlist using PEX., Leveraged 16-bit input vectors, 32-bit parallel data output with registers, and conducted Logical verification and Debugging with LVS and PEX checks. Integrated circuit into a 900um x 900um Pad Frame for optimized power line connections. RTL to GDSII Flow for a Counter Design on 45nm Technology PDK, Cadence Innovus - Genus - Tempus - Xcelium, Utilized Xcelium for simulation and Code Coverage analysis. Employed Genus for RTL to Gate Level Netlist conversion and Scan Cell insertion. Verified correctness with Conformal Logic Equivalence Checker against a Reference Design., Developed Test Mode with Full Scan, conducted Logic Tests, and generated Vectors. Implemented design flow including Placement and Routing in Cadence Innovus. Ensured Timing Closure at 100MHz in Tempus post-synthesis. Design and Implementation of an Inverter, 101 Stage Ring Oscillator, Nand4 Layout in 15nm FinFET PDK, Cadence Virtuoso, Crafted schematic and layout of Inverter, Oscillator & NAND4 leveraging Cadence Virtuoso. Executed HSpice simulations on. sp files, optimizing designs for minimal layout area and propagation delay, ensuring peak efficiency and performance., Directed the 101 Stage Ring Oscillator layout, folded to minimize metal layer connection length between the first and last Stage. Conducted DRC, LVS checks, and RC Extraction, swiftly debugging errors for seamless integration and functionality. Physical Layout design of a Configurable 10-Bit Decision Tree Custom ASIC, Cadence Virtuoso - HSpice - Calibre, Designed Layout with three metal layers for a 10-stage, 10-bit decision tree at 0.5µm technology PDK. Incorporated Microarchitecture bit slice with multi-mode operation. Implemented shared bus for reduced routing congestion and memory-mapped programming., Employed H-Tree placement to prevent Timing Failures. Validated Design using HSPICE at 1.67GHz. Tested with Diverse Datasets from UCI ML Repository. Implemented Low Power Methods, both Static and Dynamic, for efficiency.
Timeline
Research Assistant
University of South Florida
02.2024 - Current
Physical Design Intern
SmarTeq Solutions
01.2023 - 08.2023
Physical Design Engineer
Wipro Limited
01.2020 - 12.2021
Master of Science - Electrical Engineering
University of South Florida
Bachelor of Technology - Electrical, Electronics Engineering Technologies
Lovely Professional University
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