Ravi Teja Govindu
AMS Verification Engineer
San Diego,CA
Summary
Creative and innovative prospect determined to bring ideas to life through cutting-edge technology and design techniques. Team player with strong problem-solving skills to contribute effectively to projects and teams. Considers unique and unconventional solutions to deliver exceptional results.
Overview
6
6
years of professional experience
5
5
years of post-secondary education
Work History
Design Verification Engineer
Analog Devices Inc
Bengaluru, India
03.2022 - Current
- Involved as a Full chip AMS Verification engineer for ADC Products where have been working on Sigma Delta and SAR architecture ADCs.
- Established consistent and effective bug tracking processes, enabling faster resolution of reported issues by collaborating closely with design teams.
- Created reusable testbenches that reduced effort required for future projects, improving overall efficiency
- Developed comprehensive test plans based on requirements analysis, ensuring thorough coverage of all critical aspects of design functionality.
VLSI Engineer
Wipro Ltd
Bengaluru, India
11.2020 - 02.2022
- Involved as a Full chip AMS Verification engineer for Memory Products where I have worked on DDR and LPDDR.
- Optimized existing testbenches for better coverage, improving overall chip reliability and performance.
- Developed custom scripts for automating repetitive tasks in verification process, saving time and reducing human error risk.
- Conducted thorough root cause analysis on failed simulations, ensuring rapid resolution of issues and preventing future occurrences
Design Engineer
Tessolve Semiconductor Pvt Ltd
Bengaluru, India
09.2018 - 10.2020
- Maintained up-to-date knowledge of industry trends and advancements, ensuring continued relevance of analog designs to the marketplace
- Incorporated feedback from customers into design improvements, resulting in higher customer satisfaction ratings
- Developed detailed verification plans by working closely with design and system team
Trainee
Sykatiya Technologies
Bengaluru, India
05.2018 - 09.2018
- Enhanced training experience by developing comprehensive orientation programs and hands-on training sessions.
- Participated in professional development opportunities to enhance skill set, contributing to overall intern growth and potential future employment prospects
- Actively participated in team meetings, offering insightful suggestions that led to innovative problem-solving strategies
- Gained hands-on experience in various Analog and Digital Design programs, increasing proficiency and expanding technical skill set
Education
Master of Technology - Microelectronics
BITS Pilani
Pilani, India 07.2019 - 04.2021
Bachelor of Engineering - Electronics and Communication Engineering
Karunya Institute of Technology
Coimbatore, India 06.2015 - 04.2018
Skills
SystemVerilog expertise
RTL and Analog design understanding
IP and SOC verification
Verification planning
UVM methodology
Analog mixed-signal verification
Testbench development
Roles And Responsibilities
- Verification plan preparation
- Block diagram design and review using Verilog-A & Verilog-AMS
- Coding and debug
Transferable Skills
Verilog, Verilog-AMS, WREAL, System-Verilog, Perl, C, UVM (SV), Cadence Virtuoso Full Chip Simulator, Synopsys VCS-XA, LT-Spice, Adice(ADI Internal Tool)
Summary Of Experience
AMS Verification engineer with nearly 6 yrs. of experience, skilled in Verification program development, Analog Module design, Analog and mixed signal IC Module design.
Timeline
Design Verification Engineer
Analog Devices Inc
03.2022 - Current
VLSI Engineer
Wipro Ltd
11.2020 - 02.2022
Master of Technology - Microelectronics
BITS Pilani
07.2019 - 04.2021
Design Engineer
Tessolve Semiconductor Pvt Ltd
09.2018 - 10.2020
Trainee
Sykatiya Technologies
05.2018 - 09.2018
Bachelor of Engineering - Electronics and Communication Engineering
Karunya Institute of Technology
06.2015 - 04.2018