Rithik Ravula
Houston,TX
Summary
Results-driven Analog IC Layout Engineer specializing in full-custom analog and mixed-signal designs. Implemented advanced techniques in parasitic extraction and ECO updates, significantly improving current mirror matching and layout reliability. Collaborated effectively with cross-functional teams, ensuring high-quality layouts and timely project milestones.
Overview
5
5
years of professional experience
Work History
Analog Layout Engineer (Contract)
onsemi
06.2025 - 07.2026
- Designed full-custom analog and mixed-signal layouts using Cadence Virtuoso XL for advanced CMOS technologies
- Developed block-level and hierarchical layouts including floorplanning, placement, routing, and parasitic-aware optimization
- Applied common-centroid and interdigitated matching techniques to improve current mirror and differential pair matching accuracy
- Executed physical verification sign-off, conducting DRC, LVS, ERC, antenna, and density checks using Calibre for multiple analog layout blocks, ensuring compliance and quality standards
- Performed parasitic extraction (PEX) and collaborated with circuit designers during post-layout simulation and performance validation
- Implemented guard rings, shielding, DNW isolation, and EM-aware routing to improve noise immunity and reliability
- Optimized floorplanning and signal routing strategies to reduce parasitic capacitance and routing congestion, enhancing layout performance and efficiency
- Supported tapeout readiness and verification closure under aggressive project timelines
- Assisted in resolving layout-dependent effects (LDE) and parasitic-related performance degradation issues
- Collaborated with cross-functional design teams to enhance layout quality, manufacturability, and yield awareness, contributing to successful project outcomes
- Supported ECO implementation and debug activities to resolve layout and verification violations efficiently
- Contributed to analog layout development for current mirrors, differential pairs, bias circuits, and switching structures
Layout Engineer
OAG Technologies
05.2021 - 06.2023
- Applied PDN-aware layout techniques and optimized pin placement strategies for improved power integrity
- Developed block-level and hierarchical analog layouts with optimized floorplanning and routing methodologies
- Implemented shielding, guard rings, DNW isolation, and EM-aware routing techniques for analog reliability improvement
- Conducted parasitic extraction (PEX) and analyzed layout impact on circuit performance and routing parasitics
- Performed full physical verification including DRC, LVS, ERC, antenna, and density checks for sign-off compliance
- Executed ECO updates and debugged layout violations, ensuring adherence to project milestones and tapeout schedules
- Collaborated with design teams to refine layout constraints, enhancing analog layout quality
- Worked on device-level and partial-custom analog structures in advanced CMOS process technologies
- Supported post-layout verification activities, facilitating layout closure within schedule-driven environments
Education
Master of Science - Information Systems
Indiana Institute of Technology
Fort Wayne, IN04-2025
Bachelor of Technology - Electronics & Communication Engineering
Bharat Institute of Engineering And Technology
India07-2022
Skills
- Analog IC Layout
- AMS Physical Design
- Custom CMOS layout
- TSMC process technologies
- Device Matching Techniques
- Common-Centroid & Interdigitation
- Guard rings and shielding
- EM-aware routing
- LDE awareness
- DRC and LVS verification
- Antenna & Density Checks
- Floorplanning optimization
- Post-layout verification
- ECO debugging
- Cadence Virtuoso XL/GXL
- Calibre DRC/LVS/PEX
- Linux/Unix Environment
- Custom analog layout
- Hierarchical layout development
- Advanced-node layout
- Analog layout implementation
- Analog floorplanning
- Calibre verification
- Parasitic extraction
- Sign-off debugging
- ECO layout modifications
- Common-centroid matching
- Symmetry placement techniques
- Guard rings, shielding, DNW isolation
- Noise reduction techniques
- Reliability layout
- Cadence Virtuoso
- Cadence Schematic Editor
- Calibre DRC/LVS
- Linux/Unix
- TSMC FinFET
- TSMC CMOS
- Operational Amplifiers (Op-Amps)
- Voltage-controlled oscillators
- Current Mirrors
- Differential Pairs
- Bias circuits
- Latches and Switching Circuits
- Standard cell layouts
- Python for Automation
- Embedded Systems Programming
Timeline
Analog Layout Engineer (Contract)
onsemi
06.2025 - 07.2026
Layout Engineer
OAG Technologies
05.2021 - 06.2023
Master of Science - Information Systems
Indiana Institute of Technology
Bachelor of Technology - Electronics & Communication Engineering
Bharat Institute of Engineering And Technology