Rituparna Ghosh

• Build validation infrastructure for server chips using UVM framework
• Created SoC level validation strategy and test plan document with detail list of validation scenarios, and distribution of effort across multiple engineers, over 0.3, 0.5, 0.8 and 1.0 validation milestones, for on-time completion for successful SoC Tape In.
• Created tests and sequences for different swimlanes, both cluster level and SoC level flows.
• Ran level1 and level2 regression tests and monitored pass rates. Responsible for preliminary debug of failure buckets before assigning to owners.
• Worked on coverage: identify functional cover points and toggle coverage to be ported from IP level. Coverpoint coding for SoC level coverage. Fill in holes with targeted tests and sequences to have 96-99% coverage in most swimlanes, I owned.
• Familiar with die-to-die validation, using Intel's proprietary MDFI logic in server products. Currently getting ready to use UCIe spec for next generation SoP design.
• Excellent debug skills for helping others in root causing failing tests, to guarantee expedited, high-quality work across different domains.
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Worked on TI's DAC and controller validation.