Sandhya Ravindran
Summary
Verification Engineer with strong experience in CPU microarchitecture and RTL verification, currently working at Apple as part of the Load/Store Unit (LSU) DV team. Proficient in testbench development, transactor design, and feature bring-up using SystemVerilog and UVM. Previously interned at NVIDIA and Intel, with a Master’s in ECE from Georgia Tech (4.0 GPA). Skilled in performance modeling, debugging system-level issues, and developing scalable verification infrastructure
Overview
2
2
years of professional experience
Work History
CPU DV Engineer
Apple
07.2023 - Current
Load/Store Unit (LSU) Verification Team
- Developed and executed comprehensive test plans to validate functional correctness and achieve coverage goals for new Load/Store Unit (LSU) RTL features.
- Owned end-to-end integration and verification of 1 hardware prefetcher, 4 new LSU features, and multiple livelock detection widgets across the CPU pipeline.
- Triaged and debugged system-level failures including hangs and livelocks; proposed targeted mitigation strategies to improve CPU stability.
- Maintained and enhanced the LSU testbench infrastructure by developing, optimizing, and tuning Map, Dispatch, and Renaming transactors.
- Implemented new transactor functionalities to support RTL bring-up of LSU features, ensuring smoother integration and testing.
- Increased verification efficiency by modifying transactor behavior to generate more aggressive stimuli, leading to deeper functional coverage.
- Tuned transactor performance to elevate model frequency and reduce simulation runtime bottlenecks.
Education
Master of Science - Electrical & Computer Engineering
Georgia Institute of Technology
01.2023
Bachelor of Technology - Electronics and Communication Engineering
SRM Institute of Science And Technology
01.2018
Skills
- Programming: C, Shell Scripting, Verilog
- Tools Frequently Used: Epsilon, Verdi, Perforce
Internship
Nvidia - Architect Intern - GPU Projections team for Deep Learning Architecture
(May 22 – Aug 22)
Project: Designing/Calibrating the analytical throughput model (DLSIM) for performance projections of Deep Learning Communication primitives for upcoming GPUs.
● Designed test cases to observe the communication overhead in Silicon over varying message sizes for GPU clusters for all-reduce, reducescatter, all-gather and all-all for DGX-A100 and AWS multi node cluster.
● Optimized/changed the code design and calibrated performance parameters to reflect projections more closely to reality/Silicon.
Intel - Graduate Technical Intern - Software Engineering (Graph Analytics Processor)
(Sept 22 - Jan 23)
Project: Development for the software stack of a graph analytics processor, software testing, performance analysis and simulation.
● Experimental work and comparison of graph analytics benchmarks: hardware profiling analysis using Vtune.
● Analysis of results to design in house graph analytics tool – performance analysis of workload(algorithm) vs benchmark.
Timeline
CPU DV Engineer
Apple
07.2023 - Current
Master of Science - Electrical & Computer Engineering
Georgia Institute of Technology
Bachelor of Technology - Electronics and Communication Engineering
SRM Institute of Science And Technology
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