Sanjana Srinivasan
Austin,TX
Summary
STA engineer with experience in block-level timing closure, constraints development and cross-block timing analysis. Skilled in managing setup/hold criticalities, useful skew, clock transition, and PPA trade-offs. Experienced in collaborating with PnR and PD teams to optimize CTS, implement ECO fixes, and ensure silicon-ready signoff. Proficient in automating timing and STA flows using TCL and Python, with exposure to machine learning for timing path prediction. Adept at driving efficient closure while balancing technical rigor, physical constraints, and design impact.
Overview
7
7
years of professional experience
Work History
Design Engineer
NXP Semiconductors
06.2020 - Current
- Led block-level timing closure, including constraints development, STA analysis and meeting sign-off targets.
- Implemented timing ECO fixes and manual CTS interventions to resolve critical setup/hold violations and improve convergence
- Performed signal integrity analysis and addressed data and clock transition issues, ensuring robust timing closure.
- Collaborated with PnR/PD teams to understand physical trade-offs and optimize CTS for high-frequency blocks.
- Supported full-chip activities during signoff contributing to timing closure and silicon readiness.
- Assisted in tool flow improvement initiatives for new technology nodes, including automating ECO scripts to reduce manual effort.
Student Technical Intern - Automotive Microcontrollers and Processors Group
NXP Semiconductors
05.2019 - 08.2019
- Developed a complete RTL collateral for IP implementation by extracting module hierarchy using an automated crawler, enabling structured timing analysis.
- Implemented a machine learning engine to predict timing path behavior from STA reports, improving early detection of critical paths.
- Enhanced internal timing analysis tools to increase efficiency in design evaluation and closure workflows.
Education
Master of Science - Computer Engineering
Texas A&M University
College Station, Texas, United States12.2025
Master of Business Administration and Management -
Ottawa University University
Surprise, Arizona, United States12-2025
Bachelor of Engineering - Electronics and Communications Engineering
Anna University
Chennai, India05.2018
Skills
- Hardware design tools: Synopsys PrimeTime, Cadence Innovus
- Timing: STA signoff, block-level timing closure, setup/hold analysis, useful skew, clock transition management, high-frequency design, CDC awareness
- Physical Design: Clock Tree Synthesis (CTS), PnR collaboration, ECO implementation, tapeout support, PPA optimization
- Scripting and automation: TCL, Python, C/C
Timeline
Design Engineer
NXP Semiconductors
06.2020 - Current
Student Technical Intern - Automotive Microcontrollers and Processors Group
NXP Semiconductors
05.2019 - 08.2019
Master of Science - Computer Engineering
Texas A&M University
Master of Business Administration and Management -
Ottawa University University
Bachelor of Engineering - Electronics and Communications Engineering
Anna University