SANJAY MEHTA
San Jose,CA
Summary
A skilled semiconductor professional with in-depth knowledge of various aspects of semiconductor FEOL/BEOL process integration. Demonstrated leadership in team building, developing and delivering dielectric and metal film process solutions in a career that has spanned over two decades. Possess necessary experience of transferring process from R&D to manufacturing, highly adaptable and respected as a skilled problem solver.
Overview
17
17
years of professional experience
Work History
Technologist
NVM Research, Western Digital Corp
San Jose, CA
11.2021 - Current
- Led effort of transferring learning of 3D XPoint MRAM process integration challenges from Research to Development team.
- Directed process development team in defining integrated flow and process assumptions for dense 3D XPoint MRAM (1S-1R) array architecture based on knowledge of key challenges.
- Sought alignment among process, device design, characterization and system architecture teams for front up process flow option
- Worked closely with memory foundry partners to clearly identify process/tooling gaps.
- Engaged with 300mm semiconductor tool suppliers to identify best tooling options in area of (PE)ALD, and (PE)CVD dielectric thin film depositions
Senior Process Engineer
IBM Research/AI Hardware Center
Albany, NY
05.2018 - 10.2021
- Developed FEOL/BEOL dielectric thin film process solutions to meet program specific needs for eMRAM, PCM/RRAM and 2nm Gate All Around (GAA) device integration.
- Led team to develop sidewall heater process integration which resulted in 30% reduction in programming current in PCM based neuromorphic devices.
- As BEOL dielectric process tool owner, established product process control charts for dielectric process monitoring and aggressively worked with tool suppliers to meet stringent product specifications (Cp, Cpk)
- Implemented industry best practices for inline process controls of BEOL dielectric process chambers
Process Engineering Lead - IBM Assignee @ GF
ATD Group, Global Foundries Inc
Malta, NY
05.2016 - 04.2018
- Resolved tip-to-tip shorts in contact module, recovering yield loss during 7nm finFET development cycle. Received Global Foundry's Outstanding Achievement award for this accomplishment.
- Developed novel solution to mitigate cobalt migration for contact level Co metallization in 7nm finFET.
- Led team of process engineers in Advanced Technology Development (ATD) at GF to develop and deliver thin film solutions (Defect free a-Si for dummy gate, ALD SiOCN (low-k) spacer, STI and MOL Gap Fill, spatial (PE)ALD SiN for gate cap) for 7nm finFET technology
Lead Process Engineer
Advanced Dielectric Thin Films R&D, IBM Research
Albany, NY
07.2012 - 04.2016
- Developed FEOL dielectric gap fill process solutions for STI and MOL modules for 14SOI finFET technology
- Delivered throughput optimized ALD SiBCN low-k spacer process to IBM's 14nm server chip product process flow (IBM z14/z15), resulting in 8% Ceff reduction relative to ALD SiN. Received IBM's corporate award for this achievement
Process Integration Lead
FEOL Dielectric, IBM Research
Albany, NY
07.2007 - 01.2012
- Developed Defect Free STI Gap Fill solution using in-house tooling capability (SACVD) and delivered robust STI Fill process for 28LP and 20LP bulk technology nodes in manufacturing
- Developed RTCVD based thin conformal a-Si cap to serve as effective oxygen diffusion barrier during HfOx (Hi-k Gate Ox) anneal to mitigate oxide regrowth.
Advanced (PVD) BEOL Metallization Process Engineer
IBM Advanced Semiconductor Technology Center
Hopewell Junction, NY
01.2005 - 03.2006
- Identified PVD liner metallization challenges associated with BEOL integration in porous low-k dielectrics (k 2.4), brainstormed process options and developed optimized process solutions for IBM's 45nm BEOL technology.
- Demonstrated respect, friendliness and willingness to help colleagues wherever needed
Lead BEOL Process Integration, 11S2
IBM Advanced Semiconductor Technology Center
East Fishkill, NY
04.2003 - 12.2004
- Led team to BEOL integration in ultralow-k porous dielectric (k=2.4) at 65nm thin wire levels.
- Worked closely with device team to demonstrate e-beam induced device damage using 90nm (9sf) bulk HW. This definitive study resulted in fundamental shift of approach to cure low-k films from e-beam to UV.
- Identified reliability challenges of integrating in porous low-k dielectric associated with its poor mechanical properties viz. modulus and hardness (micro-trenching, PVD liner integrity, Cu migration)
- Resolved many challenges by in-house process optimization and closely collaborating with tool supplier
Education
Ph.D. - Materials Science & Engineering
Stevens Institute of Technology
Hoboken, NJSkills
- Dielectric and metal film process ownership (PVD, CVD, ALD)
- FEOL/BEOL semiconductor process integration
- Project and Resource Management
- Competitive analysis
Additional Information
- Recipient of 2020 Electron Device Society (IEEE) Paul Rappaport award
- Outstanding Technical Achievement Award 7nm Technology Feasibility Demonstration
- Outstanding Technical Achievement for 14nm finFET Technology
- Hold 100+ US and international patents in the area of semiconductor process technology.
Timeline
Technologist
NVM Research, Western Digital Corp
11.2021 - Current
Senior Process Engineer
IBM Research/AI Hardware Center
05.2018 - 10.2021
Process Engineering Lead - IBM Assignee @ GF
ATD Group, Global Foundries Inc
05.2016 - 04.2018
Lead Process Engineer
Advanced Dielectric Thin Films R&D, IBM Research
07.2012 - 04.2016
Process Integration Lead
FEOL Dielectric, IBM Research
07.2007 - 01.2012
Advanced (PVD) BEOL Metallization Process Engineer
IBM Advanced Semiconductor Technology Center
01.2005 - 03.2006
Lead BEOL Process Integration, 11S2
IBM Advanced Semiconductor Technology Center
04.2003 - 12.2004
Ph.D. - Materials Science & Engineering
Stevens Institute of Technology
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