Satya Sirasani
Austin
Summary
Experienced leader and problem-solver with a strong background in manual testing, Post silicon platform validation, performance testing, debugging, and automation testing. Proficient in PC hardware, including Intel architecture, processors, memory, SATA, SSD, USB-C, PCIE, processor and OS power management schemes. Skilled in requirement analysis, technical specifications document preparation, design and coding, application implementation, unit testing, system testing, functional testing, and regression testing. A customer-oriented team player with expertise in oral and written communication, active listening, and analytical problem- solving skills.
Overview
11
11
years of professional experience
Work History
Sr. Validation Engineer
AMD
Austin, Texas
01.2026 - Current
- Leading board validation activities for AMD data center platforms covering PCIe, I2C, and SPI interfaces during early bring-up phase.
- Executed validation of PCIe link training, LTSSM analysis, and basic compliance checks, identifying and debugging initial link instability issues.
- Performed functional validation of I2C/SMBus and SPI communication for VRs, EEPROM, and peripheral devices during platform initialization.
- Conducted early-stage Signal Integrity measurements (eye diagrams, jitter checks, waveform analysis) using high-speed oscilloscopes and protocol analyzers.
- Identified and resolved 5–10 early board-level issues related to signal integrity, protocol timing, and power sequencing.
- Collaborating with BIOS, firmware, SI, and hardware design teams to triage and root-cause interface failures.
Validation Lead
Micron Technology, Inc
Longmont, CO
01.2025 - 12.2025
- Working as a Post-Silicon Server Validation team across multiple OEM's for DDR protocols.
- Managing a Server Validation team across multiple OEM's.
- Collaborating with stakeholders to define and maintain project requirements and deliverables.
- Successfully leading the team to resolve customer issues through bug replication, root cause analysis, corrective actions/fix and validation.
- Responsible for cross-functional team communication, task execution and daily project status monitoring.
Program Manager
Intel
Hillsboro, OR
02.2021 - 11.2024
- Defined and led high-impact initiatives and process improvements for increasing quality and predictability of SW/FW releases for Post-Silicon Validation partnering with multiple ingredient teams,cross functional teams reducing the validation time by 25%,thereby accelerating the patch releases to the external customers with great quality.
- Planned and performed Serdes validation and characterization,the following was done on FPGA platform.
- Managed platform level validation for security and functional releases, across +50 Products(Includes 11th Gen client PC- Tiger Lake,14th Gen client PC-Meteor Lake,Raptor Lake).
- Debugging the customer issues using JTAG hardware debugging.
- Delivered quality results during challenging schedules, while working closely with different teams across multiple sites.
- Successfully Automated(100%) the manual validation content,thereby reducing the cost and improving the release time and reliability of the validation results.
- Successfully lead the customer programs by closely working with external customers thereby reducing the validation time by 50% and streamlining the defects.
- Established strong relationships with key customers, ensuring support for product co-validation, by implementing defect prioritization and disciplined defect management processes thereby reducing the debug time on critical issues by 20%.
- Worked on an Intel TGL processor(11th gen Client PC) and Meteor lake (14th gen Client PC).
- Collaborate with different teams to develop GPU and CPU testing coverage.
- During the course of these projects, I lead the SoC Debug and development for high-speed interfaces such as PCIe/802.3 Ethernet.
- Worked on system testing, characterization, margin analysis and optimization of high-speed PCIe,NVMe, DDR4/CXL data links over long and short channels.
- Worked on PCIe subsystem silicon bring up plans,including functional and performance tests,to Validate the subsystem for the customer faced projects to meet the customer requirements.
Electrical Validation Lead
Intel
Santa Clara, CA
06.2020 - 02.2021
- Managed a high-performing Customer Experience team, setting goals, providing guidance, and evaluating performance against established benchmarks.
- Lead Electrical Validation Debug meetings to identify risk, work on mitigation plans and implemented FPGA using SystemVerilog, which enhanced product efficiency by 20%.
- Conducted Serdes validation and characterization on the proof of concept for Altera Stratix FPGA using the loop back method.
- Managed cross functional teams including DFT,design verification,RTL integration ,FPGA, PCIe, and CXL architects, RTL developers, and physical design teams. Integrated and programmed in C to automate the validation tests, which saved up to 8 hours per week.
- Investigated and resolved complex issues with hardware/BIOS/Firmware/Operating System implementations resulting in improved performance and faster debug timelines by reducing the debug time by 40%.
- Conducted thorough root cause analyses to address different issues during validation activities, implementing corrective actions as needed.
- Executed Pre-Si validation of analog test content at IP and full chip level, including test writing and simulation.
- Conducted Silicon debug to identify electrical, functional and DFT related issues and silicon characterization to validate IO.
- Established strong working relationships with vendors ensuring smooth communication during project deployment.
Sr. Validation Lead
UST Global
12.2018 - 05.2020
- Exceeded performance goals by consistently delivering accurate results under tight deadlines, demonstrating exceptional time-management skills and prioritization abilities.
- Supported debug analysis during multiple Power-on activities on SOC Micro Processors; reducing the triage and root cause time and enabling faster issue resolution.
- Built automated test scripts to handle repetitive software testing work using Python.
- Demonstrated expertise in troubleshooting issues related to hardware compatibility, operating systems, network configurations, and third- party applications for effective problem resolution.
Programmer Analyst
Iblesoft Inc
10.2017 - 11.2018
- Tested applications and resolved complex problems throughout software development life cycle(SDLC), including preparing detailed program specifications.
- Provided ongoing support for users experiencing issues or requiring assistance with application functionality.
Validation Engineer
UST Global
04.2017 - 10.2017
- Supported manual testing including GUI, functional, regression and cycling on the latest platforms, ensuring timely delivery of high-quality products.
- Conducted root cause analysis on deviations during validation activities, enabling timely resolution of technical issues.
Programmer Analyst/Test Engineer
IDB Admins Inc
11.2016 - 03.2017
- Supported testing for multiple applications, identifying causes of issues, and providing recommendations to resolve and improve their functionality.
- Collaborated with cross-functional teams to ensure seamless integration of new features into existing applications.
- Optimized code quality through regular peer reviews, resulting in fewer defects and easier maintenance.
Programmer Analyst
Alindus Inc
08.2015 - 10.2016
- Contributed software engineering expertise in the development of products through the software lifecycle, from requirements definition through successful deployment.
- Facilitated customization of systems by encouraging software engineering team to adopt emerging standards for software application development architecture and tools.
Education
Master’s - Computer Science
University of Central Missouri
MOBachelor’s - Electronics and Communication Engineering
Vardhaman College of Engineering
Skills
- Operating System: Windows, LINUX (Fedora & Ubuntu basics) DOS and Chrome OS
- Databases: SQL Server 2012/2008 R2/2008
- Databases Tools: SSMS, SSIS, SSAS, SSRS, BIDS
- Programming Languages: C, C, Java, SQL, HTML, CSS, Java Script
- Hardware: Processor, Chipset, Mother Board,SOC,RTL,DFT,PCIe,DDR4,DDR5,NVMe, Verilog,RTL,ASIC,Serdes
Timeline
Sr. Validation Engineer
AMD
01.2026 - Current
Validation Lead
Micron Technology, Inc
01.2025 - 12.2025
Program Manager
Intel
02.2021 - 11.2024
Electrical Validation Lead
Intel
06.2020 - 02.2021
Sr. Validation Lead
UST Global
12.2018 - 05.2020
Programmer Analyst
Iblesoft Inc
10.2017 - 11.2018
Validation Engineer
UST Global
04.2017 - 10.2017
Programmer Analyst/Test Engineer
IDB Admins Inc
11.2016 - 03.2017
Programmer Analyst
Alindus Inc
08.2015 - 10.2016
Master’s - Computer Science
University of Central Missouri
Bachelor’s - Electronics and Communication Engineering
Vardhaman College of Engineering