Satya Chandra Puppala
.
Alexandria,VA
Summary
Motivated Masters graduate specializing in VLSI, adept at digital and analog circuit design, semiconductor technology, and VLSI testing. Proficient in EDA tools, with a strong problem-solving mindset and collaborative spirit. Actively seeking full-time positions to apply acquired knowledge effectively.
Overview
6
6
years of post-secondary education
Work History
Silvaco Based Cmos 4-bit Multiplier
University Of Dayton
- Project Overview: Undertook project to design and simulate 4-bit tree multiplier using GFUS 130nm process, showcasing practical application of academic knowledge.
- Implementation Techniques: Employed minimum W/L and VDD parameters to ensure optimal performance, demonstrating proficiency in implementing advanced circuit design techniques.
- Advanced Tool Utilization: Utilized Expert layout tool for layout and simulation, highlighting adeptness in leveraging advanced software for accurate implementation.
- Focus on Precision and Optimization: Maintained a high focus on meeting specifications and optimizing layout to minimize potential issues, emphasizing attention to detail.
- Hands-On Experience and Skill Development: Gained valuable hands-on experience in digital circuit design and implementation, recognizing significance of acquired skills for future projects and career advancement.
Menu Driven Test Application DE2-115
University Of Dayton
- Designed and developed a versatile system capable of diverse operations through a menu interface, integrating EPROM for data read/write functionality.
- I created a menu-driven application encompassing tasks such as LED control, EEPROM interaction, and HEX display configuration.
- Leveraged embedded system components, including the NIOS-II/e CPU, 32-bit NIOS II architecture, and UART RS-232 for real-time data transmission.
- Utilized GPIO outputs for controlling red and green LEDs, as well as 7-segment displays.
- Applied semaphores for process synchronization, enhancing operational efficiency by allowing only one process to modify resources at a time.
1- Bit Static CMOS Full Adder Circuit
University Of Dayton
- Designed and simulated a 1-bit static CMOS full-adder circuit using the GFUS 130nm process with a VDD of 1.2V.
- Implemented a minimum W/L of 130nm (160 nm or 120nm for low-voltage devices) for optimal performance.
- Utilized the Expert layout tool for precise and optimized circuit layout.
- Recognized the significance of a static CMOS full-adder circuit in digital systems and computing for binary number addition.
- I gained valuable experience in designing and optimizing CMOS circuits, along with understanding digital logic and CMOS technology principles.
Education
Master of Science - Electrical And Electronics Engineering
University of Dayton
Dayton, OH 05.2021 - 05.2023
Bachelor of Science - Electrical, Electronics And Communications Engineering
Anna University
Chennai, India 05.2016 - 05.2020
Skills
Verilogundefined
Affiliations & Accomplishments
- Cisco Certified in CCNA Routing and Switching
- Member of IEEE (2018-2019)
- Member of ISTE ( since Oct 2016 )
- Member of RMK quiz club and Campus Green Project
Timeline
Master of Science - Electrical And Electronics Engineering
University of Dayton
05.2021 - 05.2023
Bachelor of Science - Electrical, Electronics And Communications Engineering
Anna University
05.2016 - 05.2020
Silvaco Based Cmos 4-bit Multiplier
University Of Dayton
Menu Driven Test Application DE2-115
University Of Dayton
1- Bit Static CMOS Full Adder Circuit
University Of Dayton
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