Summary
Overview
Work History
Education
Skills
References
Timeline
Generic

Seann Ayers

Phoenix,AZ

Summary

Principal Engineer with over 22 years of experience in package architecture, including 2.5D and 3D designs. Expertise in heterogeneous integration, signal and power integrity, and system architecture. Proven track record in 224G SERDES channel design, mixed-signal design, and RF/microwave design. Skilled in PCB layout, routing, system integration, and verification, delivering high productivity and efficient task completion.

Overview

25
25
years of professional experience

Work History

Principal Engineer

Applied Materials
Phoenix, USA
05.2023 - Current
  • Promoted to SME/Lead for advanced AI HPC server system architecture
  • Chip-Package-Board-System R&D and Architecture
  • IEEE White Paper ECTC 2025 "32 Gbps UCIe 2.5D on Silicon Substrate"
  • 2 patent applications filed with USPTO

Lead Advanced Package Architect (SMTS)

Applied Materials
Phoenix, USA
05.2023 - 03.2025
  • 20+ Years' experience in advanced semiconductor package design & development and signal and power integrity
  • Perform R&D of advanced heterogenous integrated IC packaging working closely with world class global semiconductor customers
  • Physical design modeling with ANSYS HFSS and Siemens XPD and XSI of advanced heterogenous integrated IC packaging (2.5D and 3D)
  • Signal and Power Integrity simulation with ANSYS Electronics Desktop and Keysight ADS
  • Electrical development of Hybrid Bonding Interconnect (HBI) including electrothermal analysis with Ansys ICEPAK. Including placement of SERDES T-Coil to mitigate unwanted parasitic effect of Q performance
  • Physical design and SIPI simulation of WLFO silicon, organic and glass interposer for electrical performance evaluation
  • Physical and electrical development of 32 Gbps UCIe WLFO interconnect
  • HBM3e and HBM4 BEOL design and development for novel Silicon-Core-Substrate technology
  • HBMx DRAM stack development, RLC optimization & thermal optimization
  • White paper published by IEEE: "Signal & Power Integrity Optimization with Silicon-Core-Substrate" presented at ECTC 2024 conference
  • Design and development of Deep-Trench-Capacitor (DTC) including novel DTC design for backside power distribution network (BS-PDN)
  • 3 patent applications filed with USPTO

Senior Member of Technical Staff (SMTS)

Intel
Chandler, USA
04.2022 - 05.2023
  • Senior Architect for advanced 2.5D and 3D Interposer + Package design for SiP and monolithic FGPA
  • 16 Gbps UCIe, DDR5, 116G SERDES, 224G SERDES, PCIe7
  • Lead TSV interposer designer for 224G SERDES and package
  • Novel TSV guard-ring design (IDF submitted)
  • Perform ICN, COM, and ERL for SERDES Channel design
  • 32 GHz analog front-end (AFE) package design
  • Expert ANSYS ED (HFSS/HFS3DL/SiWave)

Senior Member of Technical Staff (SMTS)

Lightmatter
Phoenix, USA
10.2020 - 04.2022
  • Lead SIPI package design engineer for novel integrated photonics AI processor as well as silicon development working with analog and PD teams at Boston based startup
  • Led "ground-up" SIPI development of 3D and 2.5D package
  • TSV interposer design and development
  • Performed EM simulations of BEOL for RLC optimization
  • Development of silicon decoupling (MIM4/ODC)
  • Full PDN design and development Chip-Package-Board-System
  • PCIe Gen 4 channel design: IP floor-planning and silicon/BEOL layout
  • Experience with silicon PDK EM/SIPI simulation from foundry

Sr. Principal Signal Integrity Engineer

Mercury Systems AMS
Phoenix, USA
05.2018 - 10.2020
  • Technical lead for R&D department direct report to VP of engineering
  • TSV Interposer design for heterogenous IC, MCM, SiP, WLFO, PCB and stacked memory products
  • Technical SME to CTO for R&D heterogenous SiP Proposal
  • Signal & Power Integrity, High-Speed Digital, Mixed-Signal, RF & Microwave, System Architecture, Embedded Design
  • Power Integrity/PDN design: Die-Package-PCB-System Analysis
  • ANSYS Electronics Desktop (HFSS, SIwave, Q3D) and Keysight ADS expert
  • DDR5, HBM, LPDDR4, DDR4, SATA, PCIe
  • Patent-pending (US Patent 16/289190) advanced DIE-DIE topology for stacked 16GB DDR4 package
  • 16GB DDR4 Package won Gold Innovation Award from Military & Aerospace Magazine December 2019
  • Published White Paper "Understanding Broadband Behavior of TSV"

Sr. Principal Electrical Engineer II

General Dynamics
Scottsdale, USA
07.2017 - 05.2018
  • Hardware lead for advanced program
  • Responsible for all technical aspects of R&D and production design efforts
  • System/PCB/Package design
  • Space Grade (Class III, IIIA) High Density Board Design
  • Space Grade ADC/DAC design
  • Signal & Power Integrity, High-Speed Digital, Mixed-Signal, RF & Microwave, System Architecture, Embedded Design
  • Power Integrity/PDN design: Die-Package-PCB-System Analysis

Staff Engineer: Signal & Power Integrity

Amkor Technology
Tempe, USA
01.2016 - 07.2017
  • Responsible for all technical aspects of R&D and production design efforts
  • ASIC/IC Package Design: FCBGA, SiP, SoC, WLCSP, MCP, PoP, MEP
  • Signal & Power Integrity, High-Speed Digital, Mixed-Signal, RF & Microwave, System Architecture, Embedded Design
  • Power Integrity/PDN design: Die-Package-PCB Analysis
  • Current Density Optimization/Electromigration Mitigation
  • 56 Gbps SERDES Channel Design
  • LPDDR4, DDR4, DDR3, PCIe 1,2,3,4, HDMI, USB 3.1, MIPI
  • SYZ-Parameter 3D Full-Wave extraction and Analysis
  • Crosstalk Analysis: NEXT, FEXT, PSNEXT, PSFEXT, PSXT
  • Jitter Analysis & Decomposition: TIE, DCD, Stochastic, Deterministic, ISI
  • Package/PCB Stack-up, Layout, Pad-stack/Via, Dielectric Material Selection
  • Wideband Dielectric modeling & Conductor Surface Roughness Modeling
  • Expert ECAD user: ANSYS HFSS, SIWave, Q3D, NEXXIM, Cadence Sigrity Suite, Keysight Technologies ADS, Mentor Graphics Hyperlynx
  • Merit Award for R&D Design Effort

Signal Integrity Engineer

SEAKR Engineering
Centennial, USA
07.2014 - 01.2016
  • Signal Integrity Engineer and Technical Lead for various satellite programs
  • Responsible for Hardware + System-Level design from initial trade-study through prototype integration
  • Signal Integrity, Pre-route analysis, Post-route Analysis, Power Integrity analysis, EMI/EMC analysis, Clock Network Distribution Design
  • PCB Physical design, Stackup, Board material selection, Routing Rules, IPC PCB standards, Class 2, Class 3, and 3a.
  • Pad-stack/Interconnect 3D full-wave FEM simulation and analysis
  • ASIC Package design + Die-Interposer, ASIC on-package and on-die decoupling design, XTALK analysis, and Mode Conversion Analysis
  • Direct RF Sampling Multi Gigabit ADC and DAC design for ASIC. Including IP Integration, floor-planning, and on chip Clock Network Distribution
  • Jitter analysis, Jitter Decomposition, TIE Analysis, Reference Clock SSB Phase Noise Analysis
  • 28+ Gbps SERDES Channel design, Interconnect design, System level loss budget analysis, S-parameter analysis, 3rd party SERDES IP Core integration, PHY/PMA configuration, Surface Roughness Modeling, Equalization implementation: Pre-emphasis, CTLE, Multi-tap DFE
  • LeCroy SPARQ/VNA/TDR PCB/interconnect analysis, fixture DeEmbedding, Frequency and Time-domain analysis
  • PCIe 1, 2, 3, & 4, JESD204B, SerialLite, Gigabit Ethernet, SRIO, HSCSI, Fiber Channel, Aurora, I2C, SPI, Spacewire, PCI, DDR2, DDR3

Senior Digital Design Engineer II

Raytheon Missile Systems
Tucson, USA
10.2012 - 07.2014
  • Lead Signal Integrity/Embedded hardware design engineer for advanced missile program
  • High-speed SERDES channel design, i.e. PCIe, sRIO, Fiber Channel, JESD204B, Proprietary HSSB, 12.5 Gbps MGT's.
  • High speed memory interface design, DDR3, DDR2 timing. Responsible for integrating memory interface DMA from software and firmware perspective.
  • ASIC, SoC, and FPGA embedded software/firmware integration. Responsible for integrating third party SERDES IP.
  • PCB stack-up, layout, and routing design. Hyperlynx 9.1, pad-stack modeling, S-parameter analysis and modeling of high-speed multi-gigabit interconnects. IBIS-AMI modeling and Eye analysis.
  • Power integrity analysis, decoupling analysis, plane noise analysis, DC/IR drop analysis.
  • Achievement award for SERDES channel design.

Senior Baseband Engineer

Nokia Siemens Networks
Irving, USA
03.2011 - 10.2012
  • Senior Baseband designer for LTE/GSM/WCDMA Remote Radio Head assemblies. Responsible for requirement generation, development, design, integration and verification of baseband portion of BTS Remote Radio Head
  • Baseband design. High-speed RP3-01 6.125 Gbps SERDES design TX/RX equalization techniques, Pre-emphasis, CTLE, DFE, tap weight and delay generation. High-speed board interconnect analysis, pad-stack, PCB layout and critical routing, Component de-rating and electrical stress analysis
  • Altera Stratix V FPGA, Renesas ASIC, and PowerPC/Freescale Processor embedded hardware integration
  • IBIS, IBIS-AMI, S-Parameter, and HSPICE analysis and modeling
  • Python script generation for design integration and verification. JTAG boundary-scan design and debug
  • Clock/synthesizer design for mixed-signal LO's and Gigabit ADC's

Senior Electrical Engineer: Advanced Signal Processor Design

Raytheon Space & Airborne Systems
Dallas, USA
05.2000 - 04.2011
  • Lead digital CCA hardware design engineer for radar program. Signal integrity analysis. FPGA hardware integration. ASIC and SoC integration.
  • Lead engineer hardware design engineer for F-18 CD/EF ATFLIR. Targeting AA servo design. FLIR design. EO sensor design. Inertial navigation (FOG based) design. Laser TEC design. Servo control loop design.
  • Achievement award for solving servo instability ATFLIR program.
  • Achievement award for solving TVA power anomaly.
  • Achievement award for solving LASER BIT failure

Education

M.S.S.E. - Systems Engineering

Southern Methodist University
Dallas, TX
04.2011

B.S.E.E. -

Wentworth Institute of Technology
Boston, MA
08.2003

Skills

  • Signal Integrity
  • Power Integrity
  • ANSYS Electronics Desktop
  • Keysight ADS
  • High-speed design
  • Advanced packaging design
  • R&D project management
  • Electrical performance evaluation
  • Electrothermal analysis
  • Technical documentation
  • Team leadership
  • Problem solving
  • Innovation development
  • System architecture

References

  • Charles Frazer, VP of Engineering Mercury Systems, 978-302-6160
  • Neel Shah, C.O.O. Verisi Corp, 520-484-8608
  • Carl Ramey, SoC Architect, Intel, 508-864-5940

Timeline

Principal Engineer

Applied Materials
05.2023 - Current

Lead Advanced Package Architect (SMTS)

Applied Materials
05.2023 - 03.2025

Senior Member of Technical Staff (SMTS)

Intel
04.2022 - 05.2023

Senior Member of Technical Staff (SMTS)

Lightmatter
10.2020 - 04.2022

Sr. Principal Signal Integrity Engineer

Mercury Systems AMS
05.2018 - 10.2020

Sr. Principal Electrical Engineer II

General Dynamics
07.2017 - 05.2018

Staff Engineer: Signal & Power Integrity

Amkor Technology
01.2016 - 07.2017

Signal Integrity Engineer

SEAKR Engineering
07.2014 - 01.2016

Senior Digital Design Engineer II

Raytheon Missile Systems
10.2012 - 07.2014

Senior Baseband Engineer

Nokia Siemens Networks
03.2011 - 10.2012

Senior Electrical Engineer: Advanced Signal Processor Design

Raytheon Space & Airborne Systems
05.2000 - 04.2011

M.S.S.E. - Systems Engineering

Southern Methodist University

B.S.E.E. -

Wentworth Institute of Technology

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