SeokHyeon (Lucas) Kong

Innovative Undergraduate Research Assistant with a passion for critical thinking and a strong ability to distill complex theories into clear, personal insights. Enthusiastic about independently understanding and analyzing challenging concepts. Ready to take on new problems to dive in through collaboration and communication.

• Applied Machine Learning in Python (Coursera, University of Michigan)

Global Mentoring & Assisting People

• Assisted five exchange students from Europe, using English as the primary language.

Samsung Shining Star Undergraduate Program

• Participated in a short-term engineering internship program for sophomores.
• Attended seminars on each business team and toured the Samsung Semiconductor on-campus site.

Data Analysis Project Training

• Attended data analysis training provided by the Ministry of Science and ICT and the Ministry of National Defense during military service.

Korea-U.S. Student Exchange Program in the field of high-tech industry

• Issued by Minister of Trade, Industry and Energy
• Received $9,000 aid for the Fall 2024 semester

3x Dean’s List Award

• Issued by Department of Electronic and Electrical Engineering
• In recognition of academic excellence
  SP23(4.5/4.5), FA23(4.5/4.5), SP24(4.43/4.5)

Project 1: Calculator

• Developed a calculator program using RISC-V assembly language.
• Implemented 32-bit addition, subtraction, multiplication, and division without utilizing the 'sub', 'mul', 'div', or 'rem' instructions.

Project 2: RISC-V Simulator

• Created a simulator program that simulates the RISC-V microarchitecture.
• The simulator performs instruction fetching from instruction memory, decoding, executing arithmetic operations, reading data from the register file or data memory, and determining the next instruction's address.
• It reads an executable file containing multiple instructions and calculates clock cycles, the program counter (PC), and register values.

Project 3: Cache Simulator

• Developed a program that simulates an n-way set-associative cache.
• Configured the simulator to handle different associativities, cache sizes, block sizes, and replacement policies.
• Generated graphs displaying cache miss rates with varying cache configurations.

Project 1: 12-Hour Clock

• Designed a 12-hour clock module using counters and sequential logic in Verilog.
• Also implemented using an FSM (same functionality).
• Focused on precise timing transitions when the time changes.

Project 2: Opcode Calculator

• Designed a 4-bit ALU using submodules in Verilog.
• Supported operations include Bitwise NOT/AND/OR/XOR, signed addition, signed subtraction, and signed multiplication.
• The output is displayed on an FPGA.

Project 3: Elevator

• Designed an elevator system in Verilog HDL that allows people to travel between floors.
• The system receives input indicating the number of people on each floor waiting for the elevator.
• LEDs light up when people board the elevator and turn off one by one when the elevator reaches the first floor.
• Different LED colors indicate whether the elevator is moving, stopped, or at the end of its operation.

Predicting Key Regional Real Estate Prices Using Machine Learning Techniques: With an Emphasis on the Jeonsae System' 

• Published on Social Science Research Network (SSRN).
• Aimed to address and improve upon shortcomings identified in previous research.
• Data augmentation was performed using a Standard Scaler to scale data for individual regions and concatenate the data.
• This research was published after completing a course from Coursera (Applied Machine Learning in Python) and is available on SSRN: http://dx.doi.org/10.2139/ssrn.4662626.