Seungwoo Chae

Motivated electrical engineering Ph.D. student specializing in RF and Analog circuit design within the NCIC lab. Demonstrates a strong commitment to continuous learning, with patience and consistency to drive successful project outcomes.

• Amplifier Design Project

- Designed a multi-stage amplifier using Cadence Virtuoso with 45-nm process to achieve given specifications such as GBW, phase margin, noise, power consumption, output swing, and so on.

- Employed appropriate strategies for each stage and incorporated circuit design techniques to obtain desirable performance.

• Minimizing BER through PA’s Output Power Optimization

- Derived equations to obtain the minimum BER by optimizing the PA’s output power.

- Plotted with MATLAB and compared the results with Simulink baseband equivalent model.
- Submitted the manuscript to ISCAS 2025 conference.

• Audio Amplifier Design Competition (2nd place)

- Designed a comprehensive audio amplifier to have an optimal figure of merit.

- Verified each circuit block’s gain, bandwidth, and phase margin for the proper operation.

- Demonstrated it by playing music with wide frequency range to examine the performance.

• FDNIRS Circuit Simulation

- Conducted various simulations of circuit building blocks such as TIA and VCO on Cadence Virtuoso 

• IEEE UCI Soldering Workshop

- Soldered on PCB board to make an alternating LED circuit and a customized keyboard.