Shahidullah (Javed) Khandaker
Chandler,AZ
Summary
Detail-oriented Senior Process Integration Engineer with 18 years of Cleanroom Fab Semiconductor Manufacturing engineering and managerial experience.
Overview
18
18
years of professional experience
Work History
Process Integration Engineer
Intel Corporation, SPTD (Substrate Packaging TD)
03.2022 - Current
- Worked closely with process/equipment engineers to formulate and implement robust technical improvement solutions.
- Drove process improvement plan based on systematic analysis of inline/Electrical Test/yield data to meet quality and yield targets.
- Qualified multiple Intel E-lytic electroplating processes with external (Ibiden Japan) substrate manufacturing facility.
Electroplating Process Technology Development ENG
Intel Corporation, SPTD
03.2016 - 03.2022
- Qualified new processes through step-wise DOE steps for electroplating tools: Risk Assessment, Factor Screening, Window Characterization, Window Validation (including Q-time/bath life validation) and Integrated Spec Window Validation.
- Developed, communicated, and coordinated execution of process module improvement strategy for E-less and E-lytic electroplating tools.
- Worked with YE/PE to evaluate and improve process, based on analysis of data.
- Worked with Real time Defect Analysis (RDA) team and Process Development teams to identify, contain, and address excursion impacting module.
Chip Assembly Production Supervisor
Intel Corporation, ATTD (Assembly & Test TD
08.2017 - 08.2018
- Managed team of 14 workers to meet production schedule and standards in accordance with organization's policies and applicable laws.
- Managed employee training, directing work, assisting with performance appraisals, complaints and resolving problems.
- Strove for continuous improvement in worker safety and was dedicated to ensuring that each employee understands, and acts in accordance with company's safety policies.
- Wrote employee performance reviews after conducting performance review meetings.
- Investigated and implemented ideas for quality improvement and increased productivity.
- Planned, coordinated and assigned manpower to meet aggressive production schedules.
- Addressed all personnel issues promptly and professionally.
- Drove daily production activities with effective communication and leadership.
Photolithography Manufacturing Engineer
Intel Corporation, OTF (Ocotillo Technology Fab)
12.2010 - 03.2016
- Conducted root cause analysis on defective products, to improve manufacturing processes.
- Increased capacity utilization by identifying bottlenecks within production process and implementing targeted improvements.
- Led Kaizen events focused on continuous improvement within various areas of manufacturing environment.
- Improved manufacturing efficiency by implementing lean methodologies.
- Contributed to achieving safety targets by proactively addressing potential hazards and promoting strong safety culture throughout facility.
- Collaborated with cross-functional teams to develop innovative solutions for complex engineering challenges.
- Trained and mentored junior engineers, fostering culture of continuous learning and professional development within team.
- Developed strong communication and organizational skills through working on group projects.
Photolithography Manufacturing Engineer
Micron Technologies, INC
01.2008 - 05.2010
- Dispo’ed CD SEM and Overlay OOCs
- Investigated Litho tool (Scanner, TEL Track, KLA Tencor Overlay, Applied Material SEM) issues
- Evaluated manufacturing equipment performance regularly, recommending upgrades or replacements as needed to maintain optimal efficiency.
- Conducted root cause analysis on defective products to improve manufacturing processes.
- Partnered with R&D department to incorporate new technologies into existing manufacturing processes seamlessly.
- Identified appropriate methodology to shorten cycle time and achieve target margins.
Metrology Technician
Micron Technologies, INC
01.2006 - 01.2008
- Wrote and trouble-shot CD SEM measurement recipes on SEM tools.
- Reduced measurement discrepancies by implementing standardized procedures for data collection and analysis.
Education
Masters in Engineering - Microelectronics Manufacturing Engineering
Rochester Institute of Technology
Rochester, NY08.2008
Bachelor of Arts - Interdisciplinary Studies (Science & Math)
Chadron State College
Chadron, NE07.2005
Skills
- Semiconductor Processing Systems
- Lean Manufacturing
- Tool Optimization
- Process Optimization
- FMEA
- Troubleshooting
- SPC (Cp, Cpk)
- SQL
- JMP Statistical Package
- Six Sigma (DMAIC)
- Continuous Improvement
Timeline
Process Integration Engineer
Intel Corporation, SPTD (Substrate Packaging TD)
03.2022 - Current
Chip Assembly Production Supervisor
Intel Corporation, ATTD (Assembly & Test TD
08.2017 - 08.2018
Electroplating Process Technology Development ENG
Intel Corporation, SPTD
03.2016 - 03.2022
Photolithography Manufacturing Engineer
Intel Corporation, OTF (Ocotillo Technology Fab)
12.2010 - 03.2016
Photolithography Manufacturing Engineer
Micron Technologies, INC
01.2008 - 05.2010
Metrology Technician
Micron Technologies, INC
01.2006 - 01.2008
Masters in Engineering - Microelectronics Manufacturing Engineering
Rochester Institute of Technology
Bachelor of Arts - Interdisciplinary Studies (Science & Math)
Chadron State College
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