SHAILAN
San Jose,CA
Summary
SoC power expert with in-depth experience across RTL power estimation, emulation-based power analysis and power signoff . Deep expertise across Synopsys power tool chain and synthesis flows for PPA optimization, dynamic power and energy efficiency improvements.
Overview
24
24
years of professional experience
Work History
Product Engineer
Synopsys
Sunnyvale, California
06.2015 - Current
- Expert in Synopsys power products RTL through signoff stages.
- Utilized RTL power estimation tools, SpyGlass-Power and PrimePower-RTL, to enhance accuracy of power analysis.
- Engaged with sign-off power tools like PrimePower (PTPX) to ensure compliance with project specifications.
- Applied strong knowledge of emulation-based power analysis flows using ZeBu-Empower for effective power evaluation.
- Expertise in SoC power technology areas - Power Estimation and Analysis, microArchitecture Power Reduction , Analyzing PPA tradeoffs
- Uses synthesis and physical design tools such as DC, Fusion Compiler, and RTL-Architect.
- Validated power infrastructure using static power verification technologies (VC-LP) to ensure compliance with specifications.
Customer Application Engineer
Atrenta
NOIDA
06.2008 - 06.2015
- Assisted ASIA-PAC customers with Low Power flow implementation using Synopsys products to enhance design efficiency
- Created Synopsys product specifications to streamline silicon validation workflows.
VLSI Design Engineer
Wipro Technologies
Bangalore
07.2002 - 06.2005
- Executed verification of APB/AHB/DMA peripheral IPs based on comprehensive test plan
- Contributed to SoC verification team for ARM SoC in mobile phone applications
- Collaborated on SSC project for FPGA porting/re-design, re-wrote Verilog from design spec
Education
Bachelor of Engineering - Electronics
Nagpur University
05-2001
Skills
- SoC power analysis
- PPA analysis
- RTL Power
- Power Signoff
- Emulation based Power
- Workload analysis
- End to End Power flow
- Synopsys power tools
- SoC verification
- CPU Architecture
- Power Modeling
Language proficiency:
Verilog/SystemVerilog/VHDL/PERL/Tcl
Key Skills
- Expertise in RTL power reduction techniques - Sequential clock gating, datapath optimizations
- Expert in Signoff Power estimation flows - Glitch power, vector profiling, IR Drop analysis
- Familiarity with Synthesis/Backend flows for Power optimization - RTL-Architect PPA flows
- Familiarity with Power Modelling flows
- Experience in productizing new technologies, working with multi-geography multi-domain teams to implement the product strategy
Timeline
Product Engineer
Synopsys
06.2015 - Current
Customer Application Engineer
Atrenta
06.2008 - 06.2015
VLSI Design Engineer
Wipro Technologies
07.2002 - 06.2005
Bachelor of Engineering - Electronics
Nagpur University