Shairfe Muhammad Salahuddin

Responsibility:

• Understand system bottlenecks and explore/benchmark technology options for system PPA improvement
• Generate guidelines for Intel Component Research short-term and long-term goals
• Quantify the PPA benefits of existing technology components

Responsibility:

• Developing inhouse system technology co-optimization methodology for technology exploration
• PPA benchmarking of standard cells
• SRAM roadmap and DTCO beyond Intel 20A, identifying scaling and performance boosters, assist techniques
• Engagement with product team for SRAM spec definition & engagement with device and process teams for SRAM bitcell pathfinding
• Process flow-based SRAM parasitic extraction and array level PPA estimation for guiding device & process technology development
• Help executives in making data driven decision for SRAM design/process technology options
• System technology co-optimization for process and 3D package targeting
• Engaging with CAD partners to build and maintain pre-PDK 3D extraction flow for logic and SRAM
• Responsibility:

Responsibility:

• Lead a team of 8 researchers
• Maintained SRAM and Memory DTCO research activities
• Drove 3D sequential integration technology research
• Maintained external research collaborations with universities

Responsibility:

• Project lead: Technology definition to SRAM macro PPA estimation framework under 6-sigma yield
• Developed technology solutions to tackle the issues with increased bit-line and word-line resistance in scaled SRAM
• SRAM design technology co-optimization in sub 7nm FinFET, nanosheet, forksheet, CFET transistor technologies
• Proposed various scaling and circuit boosters to maximize SRAM PPA gain
• System/design space exploration of 3D sequential technology to enable high temperature annealing in the top tier devices for enhancing the performance and reliability
• Responsibilities:

Responsibility:

• SRAM bit-cell design and optimization in N7, N5, and N3 technology nodes
• System/design space exploration of 3D sequential technology to enable high temperature annealing in the top tier devices for enhancing the performance and reliability
• Responsibilities:

Responsibility:

• SRAM design technology co-optimization (DTCO) in various FinFET technologies to alleviate read and write sizing conflicts
• PVT aware read/write assist circuits and contention-free bitline for single-end read SRAM circuits in a 65nm technology
• Sub-200 mV SRAM design for implantable and wearable body sensor networks (taped-out in a 65nm technology)
• Responsibilities:

• Reflection cancellation in high-speed signalling and decoupling capacitor placement for power integrity in high-performance SoCs
• Responsibilities: