SHEFALI SHARMA

• Latest ways to solve the Data Reliability issue of SPI (Serial Peripheral Interface) Bus between Microprocessors.
• NextGen Transistors : NanoSheet Transistors.

Cache Controller Design

• Designed Cache Controller for 2-way set associative Cache for given specifications.
• Detailed explanation of the communication(read/write) among Cache Controller, CPU, Main Memory and Cache with Timing diagrams, Block diagrams, State diagrams and flowcharts.
• Included PCI bus signals with timing diagrams for I/O communications.

Static Timing Analysis

• Designed four timing paths in verilog, analyzed them using design constrained and synthesized to generate the setup and hold time reports data arrival time, data hold required time.
• Implemented and tested Divide-by-9 circuit using Verilog and synthesized it using Design Vision.
• Used Prime Time tool for Static Timing Analysis for given specifications.
• Designed 4-bit ALU in Verilog, created test vectors through PERL and verified ALU testbench through PERL generated test vectors.

Custom Router

• Designed, simulated and synthesized a 1x3 Custom Router, involving packet sender, synchronous FIFO using dual Flip Flop synchronization Style and packet receiver
• Coded and tested, through testbench, the Custom Router using Verilog HDL and VCS tool.

5-bit Linear Feedback Shift Register (LFSR)

• Designed, simulated and layout a 5-bit Fibonacci LFSR on 0.18 um process node using Cadence Virtuoso tool.
• Analyzed the LFSR for rise time, fall time, setup time, hold time and other parameters.
• Designed, simulated and layout LFSR modules such as D-Flip Flop with Set and Clear, AND, OR, NOR, XOR gates used in designing of the LFSR.
• Generated the DRC and LVS reports for the LFSR.

Other Projects:

• Design and simulated a Folded Cascode Operational Amplifier on a 0.18 um CMOS process node for a given set of specifications covering DC Open loop Voltage, Unity gain Bandwidth.
• Analyzed the Op-Amp for AC, DC Sweep and transient Analysis on PSpice tool.
• Optimized Current Gain of NPN BJT by varying Emitter and Base doping concentration using Constraint Optimization in MATLAB.
• Plotted graph of Current Gain vs Doping concentration and curve fit the graph using MATLAB functions.

• BSNL Silver Certified Engineer (Dec 2013)
• BSNL Gold Certified Engineer (May 2014)
• BSNL Platinum Certified Engineer (Dec 2014)
• C++ Language College Training (May 2015)