Shraddha KulkarnI

Electrical Engineering graduate student specializing in ASIC physical design and RTL-to-GDSII flow. Proven track record in optimizing custom standard cells and managing technology migration, ready to contribute effectively as a Physical Design Engineer.

• Teaching Assistant - HDL & Circuits II, ASU
• Semiconductor Fabrication 101 (Purdue / UT Austin / Intel)

• ASIC Acceleration for Graph Convolution Network (GCN) in Cadence Innovus [ASAP 7nm PDK], 03/25, 04/25, Designed and verified a Verilog/SystemVerilog-based GCN accelerator using sparse COO inputs and self-checking testbenches., Executed end-to-end RTL-to-GDSII physical design flow, including synthesis (Synopsys DC) and floorplanning, placement, CTS, routing, and timing closure in Cadence Innovus., Performed post-layout timing and power analysis, achieving <100 ns latency under target constraints., Optimized area, power, and timing through constraint tuning, physical optimization, and VCD-based dynamic power analysis with DRC/LVS verification.
• Design of 2-bit Ripple Carry Adder in Cadence Virtuoso, SAED 32nm PDK, 02/25, 03/25, Designed mirror-logic full adders and integrated them into a 2-bit ripple carry adder at schematic and layout levels., Completed full custom layout, meeting DRC/LVS using Synopsys IC Validator., Developed HSPICE testbenches to characterize critical-path delay, power consumption, and transition delays (LH/HL, rise/fall)., Extracted and analyzed post-layout parasitics, achieving a compact area and validated timing closure.
• RTL Design & Verification - ASCII and Numeric Display Decoder (Verilog), 01/25, 02/25, Designed Verilog HDL modules to decode ASCII characters (A-Z, a-z, 0-9) and binary decimal values into 7-segment display control signals using combinational logic., Implemented a top-level HDL controller to multiplex character sequences based on control input., Verified functionality through ModelSim/Questa simulations using targeted testbenches and waveform analysis., Conducted systematic testing, debugging, and validation to ensure correct functionality.
• RTL Design & Verification - 4-bit ALU (Verilog), 04/24, 07/24, Designed a structural Verilog 4-bit ALU using ripple-carry adders and full-adder modules, supporting arithmetic and logic operations via opcode control., Implemented signed and unsigned arithmetic, including 2's-complement subtraction using carry-in/carryout logic., Developed exhaustive Verilog testbenches to verify all ALU operations, flags (Cout, OF), and corner cases through simulation.