Shuyuan Du
Shanghai,China
Summary
Passionate individual about chip design technology, has solid background in VLSI digital design flow and 8 years working experience in EDA sign off tools. Looking for a new role as VLSI CAD/flow or EDA tool development engineer. H1B cap remains 4 years once been activated.
Overview
8
8
years of professional experience
Work History
Senior Software Engineer
Phlexing Technology
12.2023 - Current
- Transistor Level Extract Parasitic View: Implemented extract view of GloryEX, successfully stored extracted resistance/capacitance network and device instances into OpenAccess DataBase
- Developed Extracted View User Interactive Form using Skill/TCL/Python language to embed GloryEX into Virtuoso and Aether platform
- Developed GRAY BOX CELLS function for Extract View, which supports omit cells' inner parasitic information
Software Engineer
Phlexing Technology
06.2021 - 11.2023
- GloryEX Debugger: Wrote a debugger tool for user to view R/C information extracted by both GloryEX gate level and transistor level runs
- The tool can read DSPF/SPEF format netlist as input, display RC instance as edges, show the Instance Pin/Port/Substrate Pin as nodes
- Used HVtree as major data structure to organize design objects such as metal shapes, vias and instances
- Supported user's regional query, zoom in and zoom out
- Supported compare two networks side by side
Lead Product Validation Engineer
Cadence Design Systems, Inc
06.2020 - 05.2021
- Sigrity Tools: Resposible for testing XcitePI, Gds2Spd and PowerDC products
- Developed and refined diff scripts to automate daily and weekly regressions
- Conducted major tests of PowerDC when transferring GUI from MFC to QTframework meanwhile migrating engine from single core to multi cores
Application Engineer II
ANSYS, Inc
12.2017 - 08.2019
- Redhawk SC: Lead and drive the migration from Redhawk to Redhawk SC for one Tier1 customer
- Conducted the Redhawk SC correlation using a 6M instance block for static and dynamic fsdb flow individually
- Bring the static difference into 1 percent and dynamic difference into 10 percent
- Successfully solved flow flaws with rd
Application Engineer
ANSYS, Inc
07.2016 - 11.2017
- Redhawk: Conducted redhawk training for ANSYS customers
- Worked closely with designer and cad team, Supporting design technology node include 14nm/7nm/5nm
- Supporting flow include redhawk static, dynamic vectorless, dynamic VCD, signal EM, DMP
- Design blocks include CPU, NPU, Modem, DDR and Graphics
- Delivered high quality presentation documents (training slides/application notes) for ANSYS tools
Education
MSEE - VLSI/CAD
University of Southern California
Los Angeles, CA06.2016
MSEE - Transfer to USC
Ohio State University
Columbus, Ohio12.2014
BSEE - undefined
Huazhong University of Science and Technology
Wuhan, Hubei07.2014
Exchange Student - undefined
National Tsinghua University
Hsinchu, Taiwan07.2013
Skills
- VLSI
- Circuit Design
- Logic Design
- STA
- Memory Architecture
- Computer Architecture
- CPU
- C
- GIT
- Makefile
- TCL
- Skill
- Python
- Perl
- Verilog
- VHDL
- Shell
- Unix
- Redhawk
- Redhawk SC
- StartRC
- Virtuoso
Projects
Network on Chip Design, NCSim, Conformal, Primetime, Encounter, RTL to GDS, 04/16, 06/16, Designed a four core chip multithread processor consisted of variable width processor, interface and ring router. Implemented a 4 nodes router in Verilog. Testing corner cases include sending packet from three nodes to one node simultaneously., Coded RTL and Testbench in Verilog. Synthesized and optimized design to constraint clock period to 4ns. Performed static timing analysis, post synthesis simulation, logic equivalence checking, place and route using OSU 180nm library and post layout simulation. 64 Bits Variable Width Processor, NCSim, Encounter, Primetime, RTL to GDS, 01/16, 04/16, Coded in Verilog to implement a variable width processor. Supported 8, 16, 32 and 64 bits' calculation. ISA contained 23 instructions such as R type, load word, store word and branch. Resolved data dependency by Forwarding Unit, HDU and stalling logic. 1024 Bits SRAM, Virtuoso Full Custom Design, 09/15, 10/15, Completed 4 banks 1024 bits SRAM schematic and layout design. Each bank stores 16 16 = 256 bits data. Each bit data is stored in 6T SRAM structure. Tested by writing 10 sequences of 16 bits' data continuously and then read in a random order. Five Stages General Purpose Microprocessor, Virtuoso Full Custom Design, 09/15, 10/15, Drew the schematic of a five stage pipelined CPU from transistor level. Programmed in Perl to generate front end control signal, completed layout manually. Design passed DRC and LVS. Ran simulation on extracted netlist successfully. Hardware Realization of Out of Order Tomasulo Algorithm, Xilinx vivado, 08/15, 09/15, Coded a Tomasulo CPU in VHDL. Simulated design in ModelSim. Emulated using Xilinx FPGA board. Design parts include: Dispatch Unit, ROB, Store Address Buffer, Store Buffer, FRL, BPB, CFC.
Phone
+86, 152-0716-7785
Timeline
Senior Software Engineer
Phlexing Technology
12.2023 - Current
Software Engineer
Phlexing Technology
06.2021 - 11.2023
Lead Product Validation Engineer
Cadence Design Systems, Inc
06.2020 - 05.2021
Application Engineer II
ANSYS, Inc
12.2017 - 08.2019
Application Engineer
ANSYS, Inc
07.2016 - 11.2017
MSEE - Transfer to USC
Ohio State University
BSEE - undefined
Huazhong University of Science and Technology
Exchange Student - undefined
National Tsinghua University
MSEE - VLSI/CAD
University of Southern California
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