SIREESHA RANAM
Principal Solutions Engineer
Austin,Texas
Summary
Masters degree with 8 years of experience as a Physical Design Engineer. Experience in Deep submicron technologies like TSMC 3nm and greater. Handled SOC, NOC, CPU and Low Power designs. Skilled in handling large SOC designs with upto 2Ghz frequency and large blocks up to 9.6M instances. Worked on various projects for different Tech giants like AMD, Qualcomm, XilinX. Expertise in PnR implementation - Synthesis, Floor planning, Placement, Clock Tree Synthesis, SI/Crosstalk analysis, Signoff Timing Analysis, ECO implementation for timing closure and Physical Verification. Expertise in ECO at block level with signoff checks including Noise and Crosstalk Violation, Antenna, EMIR, LEC, CLP DRC and LVS. .
Overview
9
9
years of professional experience
7
7
years of post-secondary education
Work History
Principal Solutions Engineer
Cadence Design Systems
02.2023 - Current
- Currently handling a TSMC 3nm CPU block - ARM architecture with 9.8M instances and 500 macros.
- Working on different recipes for the better performance at 2Ghz frequency.
- Build custom clock tree MPCTS structure with TAP points to build the CTS which gave better results in terms of clock latency, skew, and power
- Dealt a critical block in TSMC 7nm project for a client which has 2.6M instances and 565 macros with a target frequency of 1.6Ghz from Netlist to Timing Signoff and physical verification closure.
- Handled critical setup violations on memory to registers by pulling the clock Gate, closure to memory clock pin and with Useful skew.
- Developed a TCL script to create additional PG stripes in all memory channels to reduce dynamic IR violations in Critical channels.
- Designed and prepared technical presentations and recommended solutions for client issues.
Lead Physical Design Engineer
Synapse Design Inc
07.2022 - 01.2023
- Worked on a test project for client AMD.
- Validated FULL CHIP Timing violations at top level and generated ECOs and pushed them to block/Tile level engineers.
- Pushed clocks to some ports based on the full chip Timing to some blocks.
Senior Physical Design Engineer
Qualcomm India Pvt Ltd
05.2019 - 07.2021
- Responsible for block level PNR implementation of MSM (USB and Multimedia blocks) for 2 tapeouts (TSMC 4nm and 7nm).
- Worked on multiple projects for floorplan to GDS-II implementation.
- Implemented low power designs which were both Timing and routing critical.
- Was able to freeze floorplan in a few iterations for high Macro designs.
- Handled AOB cell placement and controlled their secondary PG routing with manual edits.
- Closed Signoff Timing with Tweaker ECOs for major bucket of top violations and then used PT-SI for the remaining violations.
- Wrote TCL script to generate manual ECOs on Critical paths, which helped in smooth timing closure during Tapeout.
- Responsible for PV/CLP/FV/IR closure as well for our blocks.
- Critical hold fixes were done at Metal ECO stage by swapping metal cells to delay cells in high cell density areas/regions.
- Worked closely with PV team , to detour the Routing nets for Hold fixing without causing DRC violations during Metal Tapeout.
Physical Design Engineer
Moschip Technologies
01.2016 - 04.2019
- Worked on various projects both at in-house and client locations like AMD and XILINX.
- Involved in block level implementation from floorplan to GDS-II on 3 projects.
- Automated multiple scripts in TCL for better analysis and understanding of blocks/designs.
- Worked on TSMC 7nm project at XilinX for network on chip designs.
- Performed multiple PPA analysis to meet the targets using DC-Topo and ICC-II.
- Enabled multi bit registers at Synthesis level and used trialCTS at preCTS stage to achieve better Timing correlation and Dynamic Power.
- Applied MSCTS algorithm , using custom clock buffers (X48 and X128) for better clock driving capability as per design requirement which helped in achieving minimal insertion delay and Skew.
- Handled 'Adaptive Voltage Frequency Scaling' Design in one of the Flagship projects.
- Implemented solutions to overcome challenges related to signal integrity, electro-migration, and IR drop.
Education
Master's in ECE - VLSI -
Lovely Professional University
Punjab, India 01.2013 - 05.2015
Bachelor's in Electronics and Communication - undefined
JNTU
Hyderabad, India 01.2009 - 05.2013
Physical Design Trainee - Physical Design
Institue of Silicon Systems
Hyderabad, India 05.2001 -
Skills
Delivered high-quality floorplans by working closely with front-end designers on constraints development
Implemented innovative solutions to overcome challenges related to signal integrity, electro-migration, and IR drop
Experience in Handling Low Power Design
Hands-on experience in Parasitic Extraction and Back-annotation
STA analysis and Timing Closure Techniques
Automated several scripts in TCL
Signoff analysis and applying fixes like EMIR,FV,CLP,PV
Tool experience: ICC-II, Fusion Compiler, Innovus-Stylus , Tempus,PT-SI, Pegasus, Calibre, Qrc, Voltus, Genus
Handling UPF issues
Major expertise in Floorplaing , Place and Route , CTS and Eco implementation
Timeline
Principal Solutions Engineer
Cadence Design Systems
02.2023 - Current
Lead Physical Design Engineer
Synapse Design Inc
07.2022 - 01.2023
Senior Physical Design Engineer
Qualcomm India Pvt Ltd
05.2019 - 07.2021
Physical Design Engineer
Moschip Technologies
01.2016 - 04.2019
Master's in ECE - VLSI -
Lovely Professional University
01.2013 - 05.2015
Bachelor's in Electronics and Communication - undefined
JNTU
01.2009 - 05.2013
Physical Design Trainee - Physical Design
Institue of Silicon Systems
05.2001 -