Sommanoloth Sam Douangmala
Algonquin,IL
Summary
Experienced Field Programmable Gate Array (FPGA) design and test engineer. Involved in all phases FPGA Development Life Cycle including design, development , simulation, implementation , laboratory testing, and release via Formal Qualification Test.
Overview
36
36
years of professional experience
Work History
FPGA Design Engineer
Belcan-General Dynamic Mission System
05.2025 - Current
- Achieved successful FPGA logic design development for diverse programs through effective VHDL logic design and verification.
- Contributed to the FPGA qualification testing process for MK-48 and MK-54 programs, optimizing processor receiver and transmitter FPGA functionality. Developed proficiency in AMD/Xilinx, Altera/Intel, Microsemi /Microchip FPGA design environments and Mentor/Modelsim simulation, enhancing project outcomes.
- Designed and implemented FPGA architectures for advanced defense systems. Collaborated with cross-functional teams to integrate hardware and software solutions.
- Optimized existing designs to enhance performance, reliability, and power consumption. Developed verification plans and executed test benches for design validation.
FPGA Design Engineer
Northrop Grumman
07.2016 - Current
- Participated in FPGA design and development for multiple programs. Tasks include design, simulation, and scripting for FPGA build and simulation.
- Support, FPGA Formal Qualification Test (FFQT) process for different programs, CDP-22, CY-23, Radar Receiver FPGA, Control Indicator Unit Replacement, Antenna FPGA IMA Control. LAIRCM System Processor Replacement (LSPR) Missile Warning System Input Output (MWSIO) FPGA, APR39-Processor Support FPGA, P8 Missile Warning Sensor FPGA, and C130 (Radio Frequency Exciter, and Crystal Video Receiver Processor FPGA).
- Generated FPGA Test Description, and Test Report. Submitted as Contract Deliverables to the end government customer
- Converted Radio Frequency (Processing and User FPGA) projects from Xilinx ISE to Vivado, including design and IP updates, simulation, implementation, and generation of programing files for engineering and production tests.
- Supports software engineering to verify software tools that will be used in lab. Provide initial lab setup for multiple programs, including training SW and HW engineering for test station use.
System Hardware Design Verification Engineer
Teradyne - CDI
07.2015 - 06.2016
- Worked closely with design teams of software and hardware engineers to qualify a new digitizer of an Automatic Test Equipment (ATE) System.
- Wrote application test programs using C++ to verify different features and function of the digitizer according to the specification and beyond before approve it for new test equipment. Also, wrote test programs to receive data from oscilloscope to computer during thermal verification.
- Perform functional and timing verification of FPGA which including writing test benches for simulation. Also, verified with the application test program via read or write command. Work with power engineer to build high volt three phase test fixture for ATE System.
FPGA Design Engineer
GE Healthcare -BB7
09.2014 - 12.2014
- Worked closely with an architect, firmware engineers and design teams to design and develop the new generation of MRI Machine.
- Responsible for FPGA RTL codes of a MRI controlled modules. The design included adding new features such as data capture, diagnostic, fault detection and memory resources allocation. Perform functional and timing verification which including writing test benches for simulation.
- Product support of FPGA on the current MRI including modified some features and consolidated codes to fit a device.
Design Hardware Engineer
Nokia Siemens Network- Nova Softtech
11.2013 - 09.2014
- Worked closely with Digital Hardware Design team including developing, verification, and integration of the LTE new generation of Wireless Base Station.
- Performed Board and System Level Design Verification of Baseband Processing Cards via a Backplane, include develop test scripts to validate the function, Electrical, and Timing Analysis using oscilloscope and test equipment to measure Signal Integrity, Clock Jitter, and High Speed Digital Signal with Eye Diagram.
- Investigate the root caused related to FPGA, including codes review, function and timing simulation, on chip debug, and measured the response.
FPGA Design Engineer Consultant
Sony Tek Mission Technology-Aerotek
04.2011 - 09.2012
- Worked on the FPGA for flow cytometry and cell sorting for bioscience research data acquisition system. Successfully created identifier/marker in HDL codes for Data Acquisition System Cards in order to help software engineer identifying data stream when it has lost synch during transmitting and receiving. Put together of 2k bit packet targeted Altera Stratix III and then are transmitted via the Link port IP block to DSPs.
- Responsible for the design, simulation, and implementation of FPGA architect that interfaces with various high speed IOs such as ADCs, DACs, and Clocks. Performed verification of functional and timing which including writing test benches and debugging.
FPGA Design Engineer
Quantum Data, LLC
11.2010 - 06.2011
- Successfully designed CBUS bi-phase mark decoding for video application. Performed FPGA designed targeted Virtex5 including the architected, coded in mixed language, wrote test benches and verified using raw data obtained from Logic Analyzer. Debugged with Chipscope and FPGA Editor.
- Created backend interface for DDR2 and DAC interface protocols. Successfully designed I2S and SPI communication link between FPGA and HDMI receiver chip. Completed design documents for registers and memory map. Familiar with Apache subversion (.svn) a revision control system. Able to build FPGA using Xming and Tight VNC and program with Linux command through Ethernet protocol.
Digital Design Engineer
Photonics controls, LLC
02.2010 - 11.2010
- Responsible for product development of the next generation of the (OSMOSIS) Optical Shared Memory Supercomputer Interconnect System.
- Worked closely with the engineering team to define hardware and firmware interfaces. Integrated existing IP and custom IP into Xilinx and Altera FPGAs. Diagnosed, tested, and solved FPGA design issues on hardware using Logic Analyze tools (Chipscope and SignalTap II).
- Designed out obsolete FPGA parts and replaced them with Virtex6 families. Modified the HDL codes and created gigabit transceiver interface for Fibre Channel. Wrote test benches for functional and timing simulation.
System Hardware Develop Engineer
Teradyne
04.2008 - 11.2009
- Responsible for product development of Automatic Test Equipment digital control boards. Included FPGA development, system definition, design simulation, verification, component selection, prototyping construction, testing and field support.
- Worked closely with software engineering team to define hardware and firmware interfaces. Debugged products, tested, and solved FPGA design issues on the plat-form using logic analyzer and Chipscope
- Researched and investigated high speed digital communication devices new technology, including designing, simulating, and implementing FPGA for high speed digital communication devices.
Engineer
Magnetek-Colum Engineering
07.2005 - 12.2007
- Product development and support including partial redesign Absolute Encode for Elevator Motor Drive Control boards and Permanent Magnet Motor Elevator Control Option board.
- Redesigned obsolete FPGA and CPLD parts and replaced with different manufacturer/newer-generation components. New FPGA designs included functional/timing simulations, board-level testing, & design documentation.
Hardware & Firmware Design Engineer
Dukane Corporation
05.2000 - 06.2005
- Designed, developed, verified, and customized Beacon and TAC_DATA firmware system. Beacon is an underwater-transmitted device used a part of commercial and military aircraft data storage black box system and TAC-DATA is information tracking aircraft storage black box
- Completed migrating ASICS to Programmable Logic, including, designing, simulating, implementing, and testing.
- Designed and developed innovative solutions for advanced ultrasonic welding systems.
Analog Design Engineer
Netcom Inc.
06.1990 - 03.2000
- Designed, and developed Crystal and LC Filters.
Education
BS - Electrical Engineering and Computer Sciences
University of Illinois Chicago
Chicago, IL06.1990
Skills
- VHDL and Verilog proficiency
- FPGA programming
- Design verification
- Signal integrity analysis
- Timing analysis
- Test execution
- Regression testing
- Defect tracking
- Functional testing
Clearance
Active DoD Top Secret
Timeline
FPGA Design Engineer
Belcan-General Dynamic Mission System
05.2025 - Current
FPGA Design Engineer
Northrop Grumman
07.2016 - Current
System Hardware Design Verification Engineer
Teradyne - CDI
07.2015 - 06.2016
FPGA Design Engineer
GE Healthcare -BB7
09.2014 - 12.2014
Design Hardware Engineer
Nokia Siemens Network- Nova Softtech
11.2013 - 09.2014
FPGA Design Engineer Consultant
Sony Tek Mission Technology-Aerotek
04.2011 - 09.2012
FPGA Design Engineer
Quantum Data, LLC
11.2010 - 06.2011
Digital Design Engineer
Photonics controls, LLC
02.2010 - 11.2010
System Hardware Develop Engineer
Teradyne
04.2008 - 11.2009
Engineer
Magnetek-Colum Engineering
07.2005 - 12.2007
Hardware & Firmware Design Engineer
Dukane Corporation
05.2000 - 06.2005
Analog Design Engineer
Netcom Inc.
06.1990 - 03.2000
BS - Electrical Engineering and Computer Sciences
University of Illinois Chicago