Sumer Shende
Sunnyvale,CA
Summary
Experienced Design Verification Engineer with expertise in GPU verification and advanced cache verification. Highly proficient in UVM-based verification methodologies, and scalable verification frameworks. Goal is to contribute to industry-leading innovations in high-performance computing through functional verification, and architectural refinements.
Overview
13
13
years of professional experience
Work History
MTS Design Verification Engineer
AMD
04.2020 - Current
- Shader cache and shader core verification for AMD AI accelerator GPUs, optimizing computational efficiency and ensuring robust design.
- Validated L2 Graphics Cache subsystems across multiple mobile and console product lines, implementing coverage-driven verification for architectural robustness.
- Developed comprehensive feature verification strategies and drove IP level test plan execution.
- Led cross-functional debugging initiatives.
- Served as verification engineer, defining execution methodologies from initial RTL bring-up through final production sign-off.
- Conducted mentorship programs, helping junior engineers in test bench development, functional coverage analysis, and verification methodologies.
Component Design Engineer
Intel Corporation
08.2018 - 03.2020
- Engineered UVM-based test bench infrastructures for AI-driven ASIC architectures, integrating advanced stimulus generation techniques for scalability and automation. These results were used by multiple subsystems to help optimize performance analysis.
- Successfully automated performance profiling workflows via Python-based computational modeling, improving efficiency in large-scale design validation to bring down run times and analysis from 2 weeks to under a week.
Fellow
Teach for India
05.2014 - 04.2016
- Designed and delivered pedagogically structured learning modules, elevating conceptual comprehension among 40 underprivileged students directly and 200 students in school indirectly.
- Implemented data-driven assessment strategies, analyzing student performance metrics to optimize instructional methodologies.
Intern
ST-Ericsson
07.2012 - 07.2013
- Developed an automated testing framework for mobile handset validation using Python.
Education
Master of Science - Computer Engineering
North Carolina State University
Raleigh, NC05.2018
Bachelor of Engineering - Electrical & Electronics Engr, M.Sc. in Chemistry
BITS Pilani
India05.2013
Skills
- Programming & Verification Methodologies: UVM, SystemVerilog, Verilog, Python, C
- Domain Specializations: High-performance GPU verification, cache verification, automation frameworks
- Verification tools: Synopsys Verdi, Eclipse DVT, ModelSim, git
Research And Key Projects
- AI-Driven Surrogate Modeling for FPGA/ASIC Place & Route: Developed an AI-powered predictive model for routability and timing performance assessment, leveraging deep learning algorithms. Integrated the SUMO framework with Synopsys IC Compiler, enabling data-driven optimization for high-throughput chip design methodologies.
- Advanced LC3 Microcontroller Verification (UVM Framework) : Designed and implemented a modular, hierarchical UVM testbench tailored for accelerated verification cycles using Veloce emulation platforms.
Timeline
MTS Design Verification Engineer
AMD
04.2020 - Current
Component Design Engineer
Intel Corporation
08.2018 - 03.2020
Fellow
Teach for India
05.2014 - 04.2016
Intern
ST-Ericsson
07.2012 - 07.2013
Master of Science - Computer Engineering
North Carolina State University
Bachelor of Engineering - Electrical & Electronics Engr, M.Sc. in Chemistry
BITS Pilani
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