Summary
Overview
Work History
Education
Skills
Accomplishments
Affiliations
Certification
References
Timeline
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Sung Chung

Portland,OR

Summary

Team-oriented, adaptable, and dedicated engineer offering expertise from various experiences, from semiconductor physics, design, fabrication, failure analysis to system-level hardware design.

Overview

20
20
years of professional experience
1
1
Certification

Work History

Fault Isolation Engineer

Intel Corporation
Hillsboro, OR
10.2019 - Current
  • Conducted failure analysis on packed silicon using system boards to address the issues on logic, design rules, or design marginalities.
  • Identified and resolved process-related defects and reliability issues by collaborating with cross-functional teams.
  • Developing debug methodologies of next-generation silicon test chips and external foundries.

Component Design Engineer

Intel Corporation
Hillsboro, OR
05.2016 - 10.2019
  • Development and standardization of analog device templates (MFCs, DeCaps and Resistors) with industry-standard CAD tools and verification in different design runsets
  • Defined specification of parameterized cells for the scalable use
  • Post-development device measurement to verify the customer’s spec
  • PDK Enablement with Automated QA Process.

Process Engineer

Intel Corporation
Hillsboro, OR
07.2013 - 05.2016
  • Developed thin film dielectrics process with PEALD (Plasma Enhanced Atomic Layer Deposition) for 14nm / 10nm FinFET technology
  • Lead development forum to manage process yield and to share the learnings across FABs worldwide.
  • Achieved superior defect performance through enhanced optimization of process control system thickness and dose.

Research Assistant

Yang Lab, Purdue University
West Lafayette, IN
01.2010 - 05.2013
  • Controlled epitaxy of Si or Ge nanowire on Si substrate via Vapor-Liquid-Solid mechanism to utilize bottom-up nanowires as building blocks for integrated electrical devices
  • Aligned planar nanowires on novel structure to demonstrate into FET characteristics.

Research Engineer

IDIS Co., LTD.
Seoul, Korea
07.2004 - 12.2006
  • Developed three different models of Digital Video Recorders (DVR)
  • Designed PCB circuits for Linux embedded system and enhanced the system to qualify for Q&R test.
  • Programmed in C or Verilog for input, arbitration, and watchdog interfaces, error debugging.
  • Designed PCI interface to write MAC address in the products.

Education

Doctor of Philosophy in Electrical and Computer Engineering -

Purdue University
West Lafayette, IN
05.2013

Bachelor of Science in the School of Electrical Engineering and Computer Science -

Korea Advanced Institute of Science And Technology (KAIST)
Daejeon, Korea
08.2008

Skills

Computer Programs and Language

  • Layout CAD for design and debug: Cadence Virtuoso, Intel Cadnav, Synopsys Avalon
  • Programming: C, Shell, Python
  • PCB-level schematic application: OrCAD Capture
  • Hardware Languages: Verilog
  • Application Software: JMP, MATLAB
  • LINUX Embedded System for Circuit Control
  • CleWin3 - Optical Photomask Layout Design

Metrology and Characterization

  • Checkpoint Infrascan LTM (Laser Timing Module)
  • ThermoFisher ELITE (Lock-In IR Thermography)
  • Probe station systems: Cascade Microtech S300 Probe system, Micromanipulator 6000 with HP4156 Semiconductor Parameter Analyzer, Lakeshore cryogenic probe station CRX-4K
  • Scanning Electron Microscopy: Hitachi S-4800, JEOL JSM-6400

Device Fabrication

  • Plasma Enhanced Atomic Layer Deposition : ASM XP8
  • Chemical Vapor Deposition System : Atomate Nanowire CVD Furnace
  • Optical Photolithography: Canon PLA-501F Proximity Aligners, SUS MJB3 Mask Aligner
  • E-beam Metal Evalorator: Airco Temescal FC1800, CHA e-beam Evaporator
  • Plasma Reactive Ion Etch: Plasma Tech RIE 80
  • Thermal Treatment System: Heatpulse 610 Rapid Thermal Annealing Processor, Minipulse RTA, Protemp Horizontal Furnaces

Accomplishments

  • Hutching Creek 2 ESD positive CDM failures identification on PCIe Gen6 with detailed FAFI to isolate, understand, and fix impacted devices (Q3 2024)
  • Identifying DLVR bug on CPC and executing the back-side FIBs to prove fix on 5/5 units which gated CPC ECO tape-in and which in turn is needed to probe DLVR IP on ARL stuck-die test issues (Q1 2024)
  • Excellent work quickly root causing ARL 20% yield loss issue due to memory Vmax failures. (Q1 2024)
  • Fast root cause 3% yield loss on ARL random/atom core DLVR analog probe route issues using innovative BSPDN circuit edit + nanoprobing flow (Q1 2024)
  • Excellent demonstration of One-Intel behavior and for perfect execution on the Chapel Creek backside FIB (5/5 units pased post FIB) enabling DLVR bug fix time for re-tape-out (Q4 2023)
  • Fixed process issues impacting ARL analog circuits, and successfully debugged many yield issues weeks before ARL debug is enabled (Q4 2023)
  • Effort to shift-left ESD debug and findings to drive and validate design changes on key Hutchings Creek PCIE Gen6 testchip by (Q2 2023)
  • Dedication and cross-team collaboration to drive resolution of DDRIO blocking issue impacting QLC and GNR to enable full scan coverage deployment and path to PRQ (Q1 2023)
  • Technical support to root cause Scan critical sighting (on for 12+ weeks) by defining debug patterns through LVP/LADA hit and confirming rewvies on fixed RTL/netlist in pre-silicon environments (Q1 2023)
  • Competing a robust WWC test plan and delivering WWC Tyche debug development success criteria on schedule which will derisk ARL-P product debug (Q4 2022)
  • Collaboration with design to bring up DDR PHY and PLL rootcausing 6 critical bugs in parallel with other IPs bring-up (Q3 2021)
  • 7nm design learning from testchip IP yield debug (Q4 2020)
  • First successful 7nm yield debug of low yield (Q3 2020)
  • In recognition of outstanding effort in integrating cell content into 10nm process CPDK (Q2 2019)
  • Outstanding contributions in driving availability, improving defect performance, and optimizing dose control (Q4 2014)

Affiliations

  • Secretary of Karla Heights Home Owners Association, 07/24-
  • Treasurer of Hanmaeum Soccer Club, 01/23-
  • Group Manager of Interlude Orchestra in Metropolitan Youth Symphony, 10/21 - 05/22
  • Secretary and President of Haydon Highlands Home Owners Association, 06/19 - 07/21
  • Vice President of Purdue Electrical Engineering Korean Association (PEEKA), 09/10 - 08/11
  • Founding member of the Nine Chorus, 12/04 - 12/06
  • KAIST Chorus, Advisor (2004), Manager (2003), Head of Public Relations (2002), raised KRL 2,000,000 (USD 1,900) in sponsorship in 2003
  • Soccer club, Gyeonggi Sadan, President and Captain to lead intramural league semifinal in 2003, 03/01 - 06/04
  • Qualcomm IT Tour, San Diego & Los Angeles, CA, San Diego & Los Angeles, CA, 07/03

Certification

  • S. H. Chung, S. Ramadurgam, and C. Yang. "Effect of Dopants on Epitaxial Growth of Silicon Nanowires" Nanomaterials and Nanotechnology 4:3 (2014). (Invited Article)
  • C. Tansarawiput, S. H. Chung, Y. Xuan, L. T. Varghese, L. Zhao, X. Xu, C. Yang, M. Qi, “Horizontal Growth of Silicon Nanowire Arrays for Large-Scale Circuit Applications”, The 56th International conference on electron, ion, and photon beam technology and nanofabrication (EIPBN), 2012, Waikoloa, HI.
  • S. J. Park, S. H. Chung, B. –J. Kim, M. Qi, X. Xu, E. A. Stach, and C. Yang, “Mechanism of vertical Ge nanowire nucleation on Si (111) during sub-eutectic annealing and growth”, Journal of Materials Research, 26, 2744 (2011).
  • S. H. Chung, S. J. Park, B. –J. Kim, M. Qi, X. Xu, E. A. Stach, and C. Yang, “Effects of Annealing on Sub-Eutectic Heteroepitaxial Growth of Germanium Nanowire on Si (111) Substrate”, The 53rd Electronic Materials Conference (EMC) and Exhibition, 2011, University of California, Santa Barbara, CA.
  • XP8 Equipment Training Part I & Part II Training provided by ASM America, Inc., 2013
  • Student Travel Grants in the Electronic Materials Conference (EMC) 2011 by the TMS Foundations
  • Korea Patent, “Golf Tee”. Patent Number #20-2004-0015060, Korea, 2004.
  • Korea Chemistry Olympiad (KChO) 1999, Silver Medal, Korean Chemistry Society, Korea

References

References available upon request.

Timeline

Fault Isolation Engineer

Intel Corporation
10.2019 - Current

Component Design Engineer

Intel Corporation
05.2016 - 10.2019

Process Engineer

Intel Corporation
07.2013 - 05.2016

Research Assistant

Yang Lab, Purdue University
01.2010 - 05.2013

Research Engineer

IDIS Co., LTD.
07.2004 - 12.2006

Doctor of Philosophy in Electrical and Computer Engineering -

Purdue University

Bachelor of Science in the School of Electrical Engineering and Computer Science -

Korea Advanced Institute of Science And Technology (KAIST)
Sung Chung