Suraj Mathew

• Foundry product Segment owner for Intel 18A GAA for internal and external customer silicon
• Responsible for Customer Shuttle Intel 18A NPI and driving the performance and Yield roadmap
• Metal Gate experiments for improving Performance and Yield

• Process Integration Co-chair for contacts for Oxide Semiconductor BEOL DRAM
• Working on alternate thermally stable contacts (instead of Cu) to solve major performance and reliability bottlenecks in stacking DRAM tiers.

• Device owner Optane Atlantic Falls (CMOS) and 1242 Bow Falls CMOS pathfinding
• Developed a 1.0V/5.0V CMOS technology to drive the cross-point array cells to deliver drive and standby specifications.
• Created HV GIDL roadmap for standby power reduction and non-epi substrate introduction for lowering wafer cost.
• Non-epi substrate conversion for ATF and BWF instead of the p/p+ epi substrate.
• Process Integration Segment owner for SiGe for ESD/Spacer and Salicide modules (Jan 2019, 1-year 1 mo.)
• Module integration of sigma-cavity for SiGe embedded S/D, process optimization for low defectivity, Salicide resistance optimization, dual spacer integration for HV/LV devices.

• Multiple module ownership that extended bit-line capacitance roadmap (1y-nm to 1 α-nm) for an industry-leading 42% reduction over three nodes through metal scaling, complex integration, and use of low-k materials.
• Identified key module deficiencies/technology gaps in the process flow for reducing bit-line capacitance using proprietary integration with lower-k value materials that established the starting point for 12-nm node development.
• Developed a metal gate work-function engineered solution for improving retention and write performance of DRAM access device for 1y-nm DRAM Module.
• Presented ideas and filed patents for Micron’s next generation DRAM node that extends beyond planar DRAM to 3D -DRAM with multi-level stacking with CMOS under the Array.

1x-nm process node CMOS ownership from device design to implant engineering for meeting performance and reliability requirements.

· Worked with cross-functional teams - Design, Product Engineering, Si Modeling, and Quality to understand issues, targets, and priorities.

· Delivered periphery CMOS technology for 1x-nm DRAM that met performance requirements under severe array efficiency requirement and thermal budget constraints for sense-amplifier and row-driver devices.

· Tackled major transistor reliability (row-drivers) and mismatch (sense-amp) requirements.

· Developed a thermally stable silicide technology for contact silicide using proprietary stack materials with improved scalability down to 20-nm wide contacts.

· Extracted, monitored, analyzed, and reacted to inline data, param data and probe data to fix yield issues. Drove performance and reliability metrics to add process margin and/or reduce costs.

· Performed path-finding exploration for gate oxide scaling using high-k metal gate integration for DRAM periphery.

• Collaborative development of advanced transistor modules for DRAM CMOS technology for 45nm and beyond with several partner companies.
• Explored planar and Fin-FET CMOS (22nm) with high-K metal gates including material screening, work function tuning, and device scaling studies.
• Developed ultra-shallow junction (USJ) engineering for high performance and low leakage (for low standby power devices).
• Evaluated contact cobalt/active area nickel silicide development for high thermal stability.

Contributed as CMOS and access device engineer for three memory generations including the industry’s first 6F2 architecture DRAM built by Micron.

· Developed gate doping techniques for recess gate access device (RAD).

· Developed CMOS devices from design specifications to silicon verification, model generation, and reliability for various DRAM process nodes.

· Developed novel implant and structural changes to improve CMOS performance and scalability – innovations include dual-composite spacers for pitch and periphery CMOS, multi-level enhancement-based VT tuning.

• First job in memory design team working on the 4Mb EDO DRAM.
• Responsibilities included circuit design, layout, placement and routing, parasitic extraction, and full-chip SPICE simulation