Suriyanarayanan Ramesh

Senior Hardware Engineer

Qualcomm Technologies, Inc.

03.2020 - Current

Working on Methodology/PPA improvements at chip level for lower tech nodes - 5nm, 4nm, 3nm, 2nm
Improving SoC Power methodologies - supported multiple generations of mobile SoC, interacted with cross-functional teams (Frontend Power, Chipset, Standard Cell/IP, PostSi) for delivering better Power for mobile chipsets
Clock Signoff - DCD/Aging/Jitter for high frequency, long span clocks (DDR Subsystem) that impacts System/DRAM timing budgets - Met ddrphy IP/JEDEC targets for DCD - Expertise in Spice, Infinisim, DDR clocking schemes
Worked on Aging/HTOL mitigation for DDR interface clocks (Request/Response) - Clock Park-high/Park-low solutions, Interacted with DDR design team to have correct-by-construction aging mitigation schemes for increased stress limits to meet stringent targets. Setup custom Spice flow for jitter simulations and Infinisim for clock aging simulations
Developed scripts for quality analysis of DCD on DDR clocks to flag - nets with high delays/crosstalk, long chain of back-to-back buffers added by CTS engine for inter-clock delay balancing, clock nets routed on lower layers, low-drive cells driving high resistive nets, balance in cell to wire delay ratio to improve predictability of DCD across different corners, clock route jogs/detours and turns in staggered floorplan regions
Spiced the clock tree to model power supply induced jitter - which is used for clock uncertainty calculations of DDR to DRAM interface paths - Worked with the team to reduce the number of levels of clock tree - using custom inverters and HTREE topology based mixed solutions to achieve better clock tree Jitter. Streamlined the overall process of delivering the clock jitter data to ddrphy IP team
Established flows for Vmin analysis in Pre-Si stage. Enabled rail level Vmin analysis. Targeted Vmin improvements in chief residency modes to improve overall the days-of-use and the battery life of SoCs. Established Pre-Si to Post-Si Vmin correlation on functional/Vmin vectors to validate the flow. Gained significant understanding of system concurrency use-cases to improve chipset power.
Provided leakage scaling numbers/targets for all the rails at chip level for each product. Revised leakage targets based on in-house leakage estimator flow. Worked with the subsystem leads to ensure that the leakage targets are met.
Worked on the leakage/power KPI roll-up to the chipset power team for all the power domains/subsystems at SoC level - developed netlist/library parser to gather leakage numbers. Compared Vt distribution for each new generation of SoC and associated design and frequency changes.
Expertise with in-house leakage recovery tools to generate ECOs using Primetime-SI DMSA. Worked with methodology team to setup flows for each tech node to enable leakage recovery.
Worked with standard cell/IP teams to develop low leakage equivalent logic cells based on dominant usage and enhanced library richness for each tech node. Implementation/ECO tools helped in the leakage power improvements by using low leakage counterparts without timing impact.
Worked on custom approaches of improving the leakage recipe/qor for DDR subsystem by exploring few knobs in implementation
Executed Subsystem level CLP/FV closure for DDR. Expertise in UPF/power implementation methodologies. Solved complex issues associated with low power implementation and multi-power domain techniques. Worked closely with floorplanner on voltage area planning, power-switch placement and low power cell placement which significantly helped the signoff. Played a key role in the implementation of low power voice activation usecases accessing System Cache from CLP standpoint. Worked with the designers/front-end power team on UPF/power states cleanup to ensure smooth integration to PD
Clock tree power analysis of SoC clocks in PTPX using gate level vectors and vectorless mode - to track power KPIs. Worked with clock team on improving clock power by custom placement/grouping of clock cells.
Involved in crosstalk/noise closure, cross-corner noise analysis and fixes for DDR Subsystem. Worked on high complexity cross-corner noise closure for DDR with ever-increasing design complexity, rectilinear floorplan shapes, multiple power domains and DCVS modes.

Summary

Overview

Work History

Senior Hardware Engineer

Interim Engineering Intern

Education

Master of Science - Electrical Engineering

B.Tech - Electrical, Electronics And Communications Engineering

Skills

Misc

Targeting Methodology Roles

Timeline

Senior Hardware Engineer

Interim Engineering Intern

Master of Science - Electrical Engineering

B.Tech - Electrical, Electronics And Communications Engineering

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