Swaminathan Kathirvel
Chennai,India
Summary
Strategic Director known for high productivity and efficient task completion. Specialize in operational strategy, team leadership, and financial oversight. Excel in communication, problem-solving, and adaptability, ensuring effective team collaboration and project success.
Overview
20
20
years of professional experience
Work History
DiRECTOR ‑ TECHNiCAL
Silicic Innova Technology, Smart IOPS Inc
Chennai, India
03.2022 - Current
- PCIe UVM Verification Focus: Comprehensive UVM testbenches tailored for Xilinx UltraScale+ PCIe designs were developed, and significant contributions were made to the verification efforts of Intel PCIe P‑Tile Mapper projects, specializing in UVM verification for
- PCIe protocols across Xilinx and Intel FPGAs
- Enhancements and Innovations: Critical UVM enhancements were implemented, optimizing PCIe configurations from Gen4x4 to
- Gen4x8, significantly improving performance
- Additionally, a pivotal role was played in UVM verification of SR‑IOV implementations, ensuring robust functionality and performance
- Leadership and Team Management: A dynamic team of 15 members specializing in design and verification was managed and led
- Collaborative efforts were spearheaded to ensure successful project outcomes and achieve effective team performance
- Talent Acquisition and Development:Over 15 talented individuals from diverse academic backgrounds were identified and re‑ cruited
- Campus interview processes were orchestrated to acquire high‑potential team members
- Training and Mentorship: Comprehensive training and mentorship were provided to foster professional growth in ASIC/FPGA design verification using SystemVerilog and UVM
- A culture of continuous learning and development was cultivated within the team.
HEAD ‑ FPGA DEVELOPMENT TEAM
Jiva Sciences Pvt Ltd
Bangalore, India
08.2018 - 03.2022
- Verification Environment Creation: Extensive experiencein creatingand managing UVM verificationenvironments using SystemVer‑ ilog, UVM, Python, and TCL for Kintex 7 FPGA
- Designed initial UVM testbench frameworks for entire systems using SystemVerilog, C++, and Python, enabling comprehensive integration, verification, and validation of various designs using hardware scopes
- DSP and Image Processing Algorithm Verification: Verified numerous real‑time DSP and image processing algorithms on FPGA using UVM methodologies
- Ensured timing, testing, and debugging of FPGA, ADC boards, and hardware modules using Xilinx‑ILA/VIO and DSO
- Designed and verified critical interfaces such as UART for machine control, Tri‑Mode Ethernet MAC, and FTDI USB 3.0 for high‑speed data logging
- Conducted RTL verification for HDR image reconstruction and tone mapping
- End‑to‑End UVM Verification Solutions: Delivered end‑to‑end UVM verification solutions, notably for a 4‑channel high‑speed data acquisition system with USB 3.0 for PC data transfer
- Recruited and trained resourcesin UVM verification using SystemVerilog, fostering a knowledgeable and skilled team
- Created requirement specifications for FPGA verification through close interaction with cross‑ disciplinary teams from embedded systems, electronic hardware, optics, biology, and engineering design
- Team Leadership and Project Management: Recruited and mentored a team of six members, establishinga strong FPGA Verification vertical
- Managed project version control using Git, GitHub
- Streamlined design, development, and verification environments us‑ ingTCL.Conductedregularcodereviewsandthoroughprojectdocumentationtoensureclarityandefficiencyacrossallprojectstages.
DiRECTOR
Silicic Innova Technologies Pvt Ltd
Chennai, India
07.2014 - 07.2018
- UVM Verification of Data Acquisition System Using FPGA: UVM testbenches were developed and verified for data acquisition sys‑ tems utilizing FPGA technology
- This effort included verifying a 2‑channel 1MSPS ADC interface and conducting signal processing on
- FPGA, specifically for acquiring bovine cell data for subsequent analysis
- Real‑time verification tasks involved designing and validat‑ ing peak detection, intensity measurement, and transmission timing of acquired data, ensuring accurate extraction of parameter data transmitted via UART for offline analysis
- UVM Verification of USB 3.0 and USB 2.0 Camera Products: For USB 3.0 camera products, FPGA and hardware architectures were defined, and UVM testbenches were developed and validated
- This process encompassed rigorous hardware validation and testing of USB 3.0 camera systems
- Real‑time verification efforts included implementing and verifying various image processing algorithms on FPGA, along with developing and validating functionalities such as image cropping, the Cypress USB 2.0 interface, and synchronization units using UVM methodologies., RTL Development and Verification of Data acquisition system using FPGA:
- This design consists of 2 Channel 1MSPS ADC interface, Signal Processing on FPGA
- Acquire the bovine cell data through 2 channel 1MSPS ADC for further analysis
- Designed and Verified peak detection, Intensity and Transmit time of acquired data on realtime
- The Extracted parameter data to be sent through UART for off line analysis
- RTL Development of USB3.0 and USB2.0 Camera Products:
- FPGA/Hardware architecture definition, RTL development and verification, hardware validation and testing of USB3.0 camera prod‑ ucts
- Design and Verification of Real‑Time Image Processing using FPGA, realised various image processing algorithms on FPGA
- Developed Image cropping, cypress USB2.0 interface and synchronisation unit on FPGA
- Developed Embedded imaging based Medical Devices
FELLOW
School of International BioDesign
, India
02.2016 - 02.2016
- MEDiCAL DEViCE INNOVATiON ‑ (SABBATiCAL LEAVE FROM SiLiCiC), Conceptualising product development strategies, Product Specification Preparation, Prototyping
- Gained the ability to capture unmet clinical needs, validated the clinical needs with various stake holders related the product
- Part of organiser in Biodesign innovation Workshop to train the medical device innovators at QUT – Australia
- Enrolled Training on Business Plan Development at QUT Business School, Australia
- Products in asthma management, and in ano‑rectal care ‑ imaging device were developed
- Developed verification environment using Matlab, Python and Verilog for verifying image and signal processing algorithms.
National Institute of Technology ‑, RESERCH SCHOLAR
Trichy, India
08.2010 - 07.2014
- Developed RTL and Verified low power NoC Interconnect fabric consists of NoC Router and AXI compatible Network Interface (NI)
- Realised NoC fabric in 90nm ‑ From planning, RTL, Verification and Implementation (RTL ‑2‑ GDS) using Synopsys and Cadence Tools
- Integrated NoC subsystems targeting 90nm technology as well as in Xilinx and Altera FPGAs
- Synthesized, verified and measured the performances of Wormhole, Virtual Channel and Buffer‑less Router for NoC
- Design and verification network interface for NoC which includes tradeoff analysis of on FPGAs and 90nm ASIC
- Design and Verified a novel hybrid topology for NoC and measured the performance
- Design an enhanced Noxim simulator for NoC for Mesh, Torus, Twisted torus, Folded Torus, hybrid topologies with different routing algorithms
- Designed and verified fault tolerant router/routing algorithm for NoC
FPGA DESiGN ENGiNEER
Compton Co. Ltd
Seoul, South Korea
09.2008 - 06.2009
- DesignVerificationUsingVerilogandFPGA:Developeddesignspecificationsforimageprocessingaspectstoverifycameraproducts and reference boards using Verilog HDL
- Implemented Verilog‑based image processing algorithms for camera sensor products
- Wrote
- RTL code for Cypress USB 2.0 to interface various camera sensors, verified the design using Verilog, and simulated it in Virtex‑II FPGA
- Collaborative Interaction: Collaborated effectively with hardware, device driver, application, and firmware developers throughout the verification cycle
- Developed verification environments using MATLAB and Verilog to validate image processing algorithms
- Pro‑ vided guidance to application developers, facilitating minimal modifications to existing applications
- Verification Environment and Testing: Developed verification environments using MATLAB and Verilog for verifying image process‑ ing algorithms
- Provided guidance to application developers, ensuring minimal modifications to existing applications
- Developed an
- I2C wrapper, verified the OpenCores I2C core, and simulated it in FPGA for camera sensor configuration
- Conducted thorough testing and debugging of verification components and RTL for camera board validation.
SENiOR ENGiNEER
Sasken Communication Technologies Pvt Ltd
Bangalore, India
04.2006 - 09.2008
- Developed/Ported to verify the functionality of Various Peripherals of PIC controllers
- Improved the code/fault coverage, fixed certain bugs in the Netlist and run the regression of entire device
- Working as an individual contributor with Hardware Modeling group, developed models for I82C54 and PCI2031.Involves studying the functionality and timing of the device from the device data sheets.
- Designing a test circuit using Verilog that uses the device for which the model is being developed and simulating the circuit with test scripts
- Running Synopsys’ various QA tools on the model, and verifying that the model will work fine in a user’s simulation
- Developed test cases using Verilog and Assembly programming for USB register read/write operation, USB Reset, suspend and sleep mode functionalities, eye pattern detection and freeze operations
- Developed monitor and checkers on some specific tasks for enhancing BFM functionalities using Verilog
- Developed generator, Driver, monitor and scoreboard for entire Memory paging Module
- Module level verification has done using
- Specman with Modelsim verification environment.
PROJECT TRAiNEE
Purple Vision Technologies Pvt Ltd
Bangalore, India
01.2005 - 06.2005
- Realization of various image processing filters (Smothening, Sharpening, Errosion, Dilation and Sobel Edge detector) on Virtex II FPGA
- RTL coding and Writing Testbenches using Verilog HDL.
Education
i-Fellow - Medical Device Innovation
SCHOOL OF INTERNATiONAL BiODESiGN, AIIMS-IIT-DELHi, QUT-AUSTRALiA
Delhi, India02.2015
PhD - ECE (Network on Chip)
NATiONAL INSTiTUTE OF TECHNOLOGY - TRiCHY
Trichy, India10.2014
M.E - VLSI Design
GOVERNMENT COLLEGE OF TECHNOLOGY - COiMBATORE
Coimbatore, India05.2005
B.E - Electrical & Electronics Engg.
INSTiTUE OF ROAD AND TRANSPORT TECHNOLOGY
Erode, India05.2001
Skills
- FPGA Tools
- Xilinx Vivado
- Xilinx SDK
- Altera Quartus
- HDLs
- Verification
- Verilog HDL
- SystemVerilog
- UVM
- Specman
- On/Off-Chip Protocols
- UART
- SPI
- I2C
- AHB
- APB
- AXI
- MIPI
- LVDS
- Ez-USB20
- FTDI-USB30
- DDR2/3
- PCIe 3/4
- Logic Simulation Tools
- Cadence Xcelium
- NC-Sim
- Simvision
- Synopsys VCS
- Questasim
- Hardware Debugging Tools
- Oscilloscope
- Logic Analyzers
- ILA
- Signal Tap
- Chipscope
- Programming and Scripting
- C
- Perl
- Python
- TCL
- LaTeX
- Matlab
- Synthesis
- Timing
- Linting Tools
- Cadence Genus
- Tempus
- RTL Compiler
- Synopsys DC Compiler
- Prime Time
- Spyglass
- FPGA Development Boards/Devices
- Altera DE2
- Altera DE2_70
- Stratix
- Spartan
- ZED Board
- Arty
- Virtex
- Kintex
- Version Control
- Project Mgmt Tools
Websites
Patents
- HEMORRHOID TREATMENT DEVICE., Kathirvel Swaminathan et al., WO/2017/089982, https://patentscope.wipo.int/search/en/detail.jsf?docId=WO2017089982
- INTELLIGENT GUN FOR ARTIFICIAL INSEMINATION., Kathirvel Swaminathan et al., TEMP/E1/4638/2020-CHE, Not yet in the public domain
Awards
2015, i-Fellow 2015, School of International BioDesign, AIIMS-IIT-QUT,
2012, Graduate Students' Exchange Program (GSEP) fellowship, U of S, Saskatchewan,
2016, Participated in the Final Round of Indo - US Endowment grant, TiE San Jose, US,
2014, Portable eye system bagged 2nd Runner-up, Asia Level TiE World business plan competition,
2012, TCS research Fellowship, National Institute of Technology - Trichy, 2014,
Rs 25 Lakhs Startup Fund, CEDI, NIT, Trichy
Publications
- Design of a novel energy efficient topology for maximum magnitude generator, IET Com. Dig. Tech., pp. 1-9, 2015
- Design and verification of an efficient WISHBONE-based network interface for network on chip, Elsevier's Computers & Electrical Engineering, 40, 6, p.1838-1857, 2014
- High Speed Low Power Ping Pong Buffering Based Network Interface for Network on Chip, Journal of Low Power Electronics, 9, p.322-331, 2013
- High Speed Generic Network Interface for Network on Chip Using Ping Pong Buffers, International Symposium on Electronic System Design (ISED 2012), pp.72-76, 19-22 Dec. 2012, Kolkata, India
- Design of a low power network interface for Network on chip, 26th Annual IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), pp.1-4, 5-8 May 2013, Regina, Canada
- A Novel Hybrid Topology for Network on Chip, IEEE 27th Canadian Conference on Electrical and Computer Engineering (CCECE 2014), 4-7 May 2014, Toronto, Canada
- Enhanced Noxim simulator for performance evaluation of network on chip topologies, International Conference on Recent Advances in Engineering and Computational Sciences, pp.1-5, March 6-8, 2014
Academic Activities
- 2016, Technical Expert, Biodesign Process - Medical Device Innovation, QUT, Australia
- 2016, Technical Expert, Advised VLSI Projects for Institutions, NIT-Trichy, NIELIT-Calicut, PSG-Coimbatore, IIIT-Trichy, India
- 2017, Technical Expert, Essential Ingredients of a successful MedTech Startup, VIT, Vellore, India
- 2020, Keynote Speaker, Innovation in Medical Devices and Impact of Internet of Things in Tele health in Rural India, RMKEC, India
- 2016, Technical Expert, Medical Device Innovation - How to form a successful Medtech Start up, IITM, Chennai, India
- 2014, Guest lecture, Low power techniques on System on Chip, NIT, Trichy, India
- 2017, Guest Speaker, Network on Chip Basics, VIT-V, VIT-C, India
- 2020, Session Chair, International Conference on Cutting Edge Technologies in Electrical, Communication, Embedded System and Soft Computing Techniques, SEC, Trichy, India
- 2021, Session Chair, International Conference on Intelligent Computing, Smart Communication and Network Technologies, RMKEC, India
- 2014-2023, Guest Speaker, Delivered more than 60 Tech Talk on Network on Chip, IoT applications in Medical Devices and Agriculture, Medical Device Innovation, India
Coursework
- Udemy - High-Level Synthesis for FPGA.
- Cadence - Cadence RTL-to-GDSII Flow v3.0
- Cadence - Advanced Synthesis with Genus Stylus Common UI v19.1
- Cadence - Low-Power Flow with Innovus Implementation System v20.1
- Cadence/Udemy - VSD - Static Timing Analysis
- Udemy - VSD - Physical Design Flow
Timeline
DiRECTOR ‑ TECHNiCAL
Silicic Innova Technology, Smart IOPS Inc
03.2022 - Current
HEAD ‑ FPGA DEVELOPMENT TEAM
Jiva Sciences Pvt Ltd
08.2018 - 03.2022
FELLOW
School of International BioDesign
02.2016 - 02.2016
DiRECTOR
Silicic Innova Technologies Pvt Ltd
07.2014 - 07.2018
National Institute of Technology ‑, RESERCH SCHOLAR
08.2010 - 07.2014
FPGA DESiGN ENGiNEER
Compton Co. Ltd
09.2008 - 06.2009
SENiOR ENGiNEER
Sasken Communication Technologies Pvt Ltd
04.2006 - 09.2008
PROJECT TRAiNEE
Purple Vision Technologies Pvt Ltd
01.2005 - 06.2005
i-Fellow - Medical Device Innovation
SCHOOL OF INTERNATiONAL BiODESiGN, AIIMS-IIT-DELHi, QUT-AUSTRALiA
PhD - ECE (Network on Chip)
NATiONAL INSTiTUTE OF TECHNOLOGY - TRiCHY
M.E - VLSI Design
GOVERNMENT COLLEGE OF TECHNOLOGY - COiMBATORE
B.E - Electrical & Electronics Engg.
INSTiTUE OF ROAD AND TRANSPORT TECHNOLOGY
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