Lead Root-Cause-Engineering team to solve critical issues impacting Dell portfolio of servers.
Fixed systemic field issues which led to reduction in warranty cost, dispatch rates, customer calls.
Led multi-discipline tiger team to improve factory first-pass-yield by 25%.
Lead system engineer: designed from ground up modular infrastructure (PowerEdge MX7000, FX2, VRTX) that integrate compute nodes, shared storage, networking switch, and PCIe cards.
Validated and optimized PCIe, DDR4 channels for maximum margins.
Innovated redundancy design enabling fault tolerant of shared storage architecture in PowerEdge VRTX.
Author Dell FRU Architecture specification: standard framework for all Dell FRU devices.
Authored Dell white paper on PowerEdge modular servers: improved customer experiences and generated sales.
Authored behavior specifications for development of FPGA components.
Collaborated with cross-functional teams on design reviews and test plans.
Board Design Engineer
Hewlett-Packard
07.1997 - 10.2003
Designed schematic and PCB board for 8 CPU ProLiant DL760.
Designed motherboard for ProLiant DL560.
Designed motherboard for consumer product: Compaq Presario 5600 PC.
Led rigorous schematic and layout design reviews.
Solved complex multi-board system issues that improved overall system performance.
Analyzed and interpreted customer requirements to develop engineering solutions.
Developed high-quality engineering designs and plans to meet industry standards.
Board Design Engineer
IBM
02.1992 - 07.1997
From marketing requirements through design, validation, and mass production, designed successful mainstream Commercial Desktop IBM PC that became industry standard platform for businesses.
Developed troubleshooting methodologies that helped reduce customer returns by 20%.
Fixed stop ship issues encountered during New Product Introduction at manufacturing facilities world-wide.
Mainframe Validation Engineer
IBM
06.1989 - 02.1992
Developed rigorous validation plan and test methodology that discovered design flaws in ES/9000 mainframe computer.
Created automated test scripts that reduced test cycle time by 50 percent.
Built test matrix that improved test execution and test coverage by 100 percent.
Education
Bachelor of Science - Electrical Engineering
University of Wisconsin - Madison
Madison, WI
05.1989
Skills
Schematic capture
Allegro PCB layout
Code in Python
Create Linux scripts
Problem solving
Triage HW issues
Oscilloscope
Logic analyzer
Signal integrity design rules
Computer architecture
PCIe topology
BMC architecture
Component Selection
Hardware Integration
Hardware and Software Optimization
Quality Control
Specifications Writing
Additional Information
PATENTS
, 7, 496,747 Redundant Link Mezzanine Daughter Card.
8,285,893 System and Method for adaptively setting connections to I/O hubs within an information handling system.
SENIOR PRINCIPAL BUSINESS INTELLIGENCE MANAGER at DELL Technologies (DELL EMC + Dell Entities)SENIOR PRINCIPAL BUSINESS INTELLIGENCE MANAGER at DELL Technologies (DELL EMC + Dell Entities)
Principal Software Engineer – Performance Engg at Dell Technologies Inc, Dell International ServicesPrincipal Software Engineer – Performance Engg at Dell Technologies Inc, Dell International Services