Tianwei Sun
Gilbert,AZ
Summary
Passionate semiconductor packaging Project Manager leading successful New Product Introduction (NPI) projects overseeing all phases from product POC, design, validation, certification to high volume production with a focus on enhancing product quality & cost and minimizing time to market. Eager to lead innovative or continuous improvement projects for cost reduction and deliver measurable outcomes. No sponsorship needed
Overview
11
11
years of professional experience
2
2
Certifications
2
2
Languages
Work History
NPI Technical Project Manager, Packaging
Intel
08.2022 - 09.2025
- Led Global team and delivered 3 flagship Ethernet Controller Products on time with over 20 million total volumes. Successfully completed 3 test chips development and assembly on time enabling urgent new foundry node technology assessment (delivered within 3 months).
- Streamlined project delivery by implementing waterfall and Agile methodologies and enhancing team communication.
- Guided component (PCB, Caps, MC) design and guided component sourcing and procurement process. Collaborated with commodity engineers to reduce component cost by 50%.
- Championed continuous improvement initiatives within the team by analyzing past performance data to identify areas for growth and cost reduction opportunities.
- Conducted technical risk analysis (TRA, FMEA) and performed DOE to improve design parameters reduce risk level to 1-low. Directed qualification activities (TC, uHAST, HTS…), directed urgent failure analysis on defects.
- Worked with vendors on assembly process improvement to enhance production yield to 99.5% (DFM, SPC) per capability.
- Managed project schedule. Performed logistic risk analysis and critical path management resulting in all milestone achievement on time and project completion with 3-5 weeks pull in all projects.
- Managed project cost: Realized $0 budget overrun in all projects, negotiation with vendor on component and NRE prices, resource leveraging (save>$500K).
Technical Project Leader, IC Packaging Engineer
NXP Semiconductor
06.2014 - 07.2022
- Spearheaded innovative solutions to complex product technical challenges, surveyed with vendors for better material and components, consistently driving projects forward for better performance and cost reduction.
- Identified new material with better heat dissipation (improved by 3X) and enabled unit cost reduction (30%) and environmental regulation compliance (impacted >10 million business).
- Performed DFM, optimizing product assembly process (e.g. material dispensing, curing profile, assembly equipment arranging) to optimize packaging design and assembly process (yield enhanced to 99.8%).
- Continued leading team scaling new materials to >10 more product lines.
Education
Master of Science - Mechanical Engineering
Arizona State University
Tempe, AZ05.2014
Skills
Project Management
Certification
Lean Six Sigma Green Belt
Patents
- Patented a new wafer back metal plating stack for our packages with sintered Ag paste die attachment.
- Patented a new field plate structure in GaN wafers to enable higher accuracy thermal measurement.
- Patented an air cavity package with containing peripherally encapsulated dies and fabrication method.
Work Availability
monday
tuesday
wednesday
thursday
friday
saturday
sunday
morning
afternoon
evening
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Timeline
NPI Technical Project Manager, Packaging
Intel
08.2022 - 09.2025
Technical Project Leader, IC Packaging Engineer
NXP Semiconductor
06.2014 - 07.2022
Master of Science - Mechanical Engineering
Arizona State University