Summary
Overview
Work History
Education
Skills
Expertise
Timeline
Generic

Vijay Narreddy

Austin

Summary

To attain a position that will enrich my skills in the field of VLSI and to be focused, flexible in the objectives assigned, while using the knowledge attained through my experience.

Proactive and goal-oriented professional with excellent time management and problem-solving skills. Known for reliability and adaptability, with swift capacity to learn and apply new skills. Committed to leveraging these qualities to drive team success and contribute to organizational growth.

Overview

21
21
years of professional experience

Work History

Sr. Staff Engineer

Synopsys
02.2021 - Current
  • Participated in formal internal design reviews of proposed products and components.
  • Developed cost estimates and project specifications for proposals.
  • Provided input to team lead regarding areas for process and procedural improvement.
  • Reviewed technical drawings developed by CAD technicians and drafters.
  • Developed positive working relationships with stakeholders to effectively coordinate work activities.
  • Developed and implemented procedures to verify compliance with engineering standards.
  • Created detailed reports on engineering activities and findings.
  • Implemented new strategies to reduce costs and improve efficiency of engineering team.
  • Collaborated with other departments to facilitate successful project completion.
  • Conducted research to identify and evaluate new technologies and concepts.
  • Assisted in developing cost-effective solutions to engineering problems.
  • Implemented automated systems to improve accuracy and efficiency of engineering processes.
  • Analyzed and interpreted data to identify trends and recommend improvements.
  • Analyzed and interpreted customer requirements to develop engineering solutions.
  • Conducted technical evaluations of engineering designs and test results.
  • Documented and developed engineering procedures and processes.
  • Developed comprehensive engineering documents for all projects.
  • Trained and mentored junior engineers, providing guidance and direction.
  • Monitored and evaluated engineering performance to recommend improvements.
  • Wrote, reviewed and edited technical document in accordance with template requirements.

Contractor from Ascent Consulting

Synopsys India Private Limited
08.2013 - 12.2016
  • Debugging mismatches of the internal Benchmarks designs with the implementation of “optimization for VCS runtime performance improvement”.
  • Supporting VCS customers.
  • Writing test plans for the new features testing in VCS and VC Static
  • Received appreciations from many customers for excellent support.
  • Highly appreciated by Senior Management for these efforts.
  • Synopsys is one of the leading EDA Supplier, providing the global semiconductor market with the software, IP and services used across the stages involved in ASIC development flow.

Corporate Applications Engineer (II)

Synopsys India Private Limited
06.2006 - 04.2013
  • Travelled for three months to the headquarters in Mountain View, CA, California. Worked with customers who were at critical stages of their verification flow. Helped them with quick workarounds and solutions for faster turnaround time. Highly appreciated by Senior Management for these efforts.
  • Owned VMC (Verilog Model Compiler) related to encryption and provided feedback on the functional specs by R&D. Helped the team regarding the queries related to VMC, while handling customer queries as well.
  • Specialized in debugging complex simulation environments of customer from across the globe getting appreciation from the management frequently.
  • First contact for everything related to the linting tool, LEDA. Worked extensively in complex customer environments and helped them get closure to the lint free code.
  • Onsite tool deployment and customer evaluations on multimillion gate designs (RTL & GLS). Appreciated for the role in a successful evaluation of VCS in a multimillion $ deal.
  • Worked with R&D on new feature support and bug fixes – test plan creation
  • Testing and validation of new features – writing unit level tests and benchmark debugging.
  • Developed expertise in debugging multimillion gate designs involving verification environments built around Verilog, SystemVerilog.
  • Appreciated for working extra hours during a major evaluation of VCS which was finally a win for Synopsys
  • Multiple customer positive feedbacks on the support quality I provided.
  • Synopsys is one of the leading EDA Supplier, providing the global semiconductor market with the software, IP and services used across the stages involved in ASIC development flow.
  • CAE responsible for some internal optimization features.
  • Global support for VCS, SV, VMM and other technologies
  • Internal SolvNet article submission on various topics.
  • Internal bug findings
  • Error message reviewing, doc reviewing and new feature testing.
  • Owned the feature related to ATE (Automatic Testcase extraction) and provided feedback on the functional specs by R&D.
  • Helped Leda customers in writing custom rules using Versl/VRSL for linting their design as per their requirements.
  • Worked with RnD by creating Functional specs for CDC (Clock Domain Crossing) rules in Leda.

Internship

Synopsys India Private Limited
06.2005 - 06.2006
  • Adding the in-house available test cases to regressions and Benchmarks.
  • Performing Sanity testing for VCS/VCS-MX patches/releases.
  • Validated various RTL and GLS designs in VCS/VCS-MX

Education

PG Diploma - VLSI Designs

Sandeepani Institute
Bangalore
06.2005

Bachelor’s Degree - Electronics & Communications engineering

Madurai Kamraj University
Tamilnadu
06.2004

Skills

  • Skilled in digital design languages: SystemVerilog, VHDL, Verilog
  • Understanding of UPF standards
  • UVM methodologies
  • Experience with VCS and Verdi for simulation and verification
  • Experienced in scripting with TCL and Python
  • Proficient in resolving complex issues
  • Skilled in utilizing Verdi and DVE for effective debugging

Expertise

  • Proficient with the coverage driven verification environment for unit and system level using Verilog and SystemVerilog.
  • Hands-on experience in verification of digital logic using Verilog, VHDL.
  • Worked in different verification environments of premium customer’s and helped them debug to isolate the problems they face with respect to EDA tool, their environments and RTL code.
  • Good Communication and interpersonal skills with fast understanding of the Project requirements which helps in coordinating between different business groups.
  • Demonstrated ability to quickly analyse and debug complex verification environments under tight schedules.
  • Debugging experience with multi million gate RTL and GLS designs.
  • Expert in the leading EDA tools e.g. VCS, VCSMX, Leda/VC-Lint.
  • Experience in good documentation & article writing skills.
  • Demonstrated ability to quickly learn verification techniques; excellent capability to complete and deliver complex verification env under tight schedules; excellent team player with demonstrated capability to work effectively with customers and RnD groups.

Timeline

Sr. Staff Engineer

Synopsys
02.2021 - Current

Contractor from Ascent Consulting

Synopsys India Private Limited
08.2013 - 12.2016

Corporate Applications Engineer (II)

Synopsys India Private Limited
06.2006 - 04.2013

Internship

Synopsys India Private Limited
06.2005 - 06.2006

Bachelor’s Degree - Electronics & Communications engineering

Madurai Kamraj University

PG Diploma - VLSI Designs

Sandeepani Institute