Summary
Overview
Work History
Education
Skills
Accomplishments
Timeline
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VINOD SAKE

San Jose,CA

Summary

Over 8 years of professional experience in fields varying from software to hardware. Motivated for generating high quality RTL by creating a compressive test plan and reusable verification environment. Looking for challenging and competitive opportunities in design and verification roles

Overview

10
10
years of professional experience

Work History

Sr Silicon Design Engineer

AMD
San Jose, CA
08.2021 - Current
  • Constructed a testbench from scratch tailored specifically for the DPU block, enabling interaction with the PCIE Host, User Fabric, and Ethernet Module
  • Developed a resilient UVM testbench architecture designed for reuse across chip-level projects and other teams
  • Implemented a testbench capable of both driving tests and calculating performance metrics
  • Assisted with debugging during TB bring-up and subsequent phases on silicon
  • Played a pivotal role in identifying critical bugs related to functionality, performance, and power prior to tape-out

Pre-Si Valid/Verif Engineer

Intel
Santa Clara, CA
11.2018 - 08.2021
  • Verifying features such as coherency, RDT (Resource Director Technology), UPI (Ultra Path Interconnect) on single and multiple socket emulation environment
  • Good experience with x86 microcode debug and quickly ramped up on new learnings
  • Worked on Tensor Processing core verification by developing UVM sequences and tests to verify core operations using constraint random stimulus
  • Setup RAL (Register Access Layer) at subsystem to verify correctness of registers
  • Enabled compression & decompression IP UVM environment at TPC sub-IP level by Modeling reference checker for end-to-end testing of data
  • As a programming enthusiast, worked with software team to develop a tool which abstracts Simics (full-system simulator) and emulation for user to run tests
  • Reduced precious emulation cycles by checking the correctness of test code on software models

Software Engineer Intern

Intel
San Diego, CA
03.2018 - 09.2018
  • Developed an Automation tool using for log analysis of cellular modem (LTE/3G) protocols tests
  • Reduced 60% of manual effort by providing preliminary findings on issues using the tool

Teaching Assistant

PSU
Portland, OR
09.2017 - 03.2018
  • Embedded Operating Systems (ECE - 362) (C/C++, OS)
  • Industry Design Processes (ECE - 411) (Arduino, Embedded C)

Application Validation Engineer

Wipro Technologies
Hyderabad, TA
07.2014 - 08.2016
  • Verified Siebel CRM by implementing automated scripts that improved productivity by 60%

Education

Master of Science - Computer and Electrical Engineering

Portland State University
09.2018

Bachelor of Science - Electrical and Computer Engineering

Osmania University
06.2014

Skills

  • HDL/HVL: Proficient in Verilog, System Verilog, UVM
  • Programming: Competent in C, C, Python, Makefiles
  • Tools: Questa/ModelSim, Xilinx Vivado, Synopsys VCS
  • Architecture: CPU, GPU, DDR, Cache, PCIE
  • Emulation: Mentor Veloce and Xilinx FPGA
  • Protocols: AMBA AXI, Cellular LTE/3G protocols, PCIE

Accomplishments

  • Was honored with the Excellence Award for outstanding contributions in design verification by the Corporate Vice President at AMD

Timeline

Sr Silicon Design Engineer

AMD
08.2021 - Current

Pre-Si Valid/Verif Engineer

Intel
11.2018 - 08.2021

Software Engineer Intern

Intel
03.2018 - 09.2018

Teaching Assistant

PSU
09.2017 - 03.2018

Application Validation Engineer

Wipro Technologies
07.2014 - 08.2016

Master of Science - Computer and Electrical Engineering

Portland State University

Bachelor of Science - Electrical and Computer Engineering

Osmania University

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VINOD SAKE