Vishakh Balakuntalam
San Diego,CA
Summary
Dynamic engineer with extensive experience at Qualcomm, specializing in micro-architectural modeling and performance analysis. Proven track record in enhancing GPU and DDR subsystem performance through innovative architectural improvements and benchmarking tools. Proficient in C/C++ and skilled in collaborative problem-solving, driving impactful results in high-stakes environments.
Overview
9
9
years of professional experience
Work History
Engineer, Staff | GPU Subsystem, QCT
Qualcomm
San Diego, CA
09.2022 - Current
- Leading micro-architectural exploration, modeling and performance analysis of memory subsystem in GPU
- Developed L1 and L2 cache performance models inside GPU subsytem
- Created a waveform analyzer tool to extract metrics for benchmark performance analysis
- Conducted architectural exploration to enhance GPU scalability
- Leveraged expertise in DDR architecture to propose micro-architectural improvements for optimized interaction between GPU and DDRSS, resulting in enhanced performance
- Performed competitive analysis to identify shortcomings of our architecture compared to competitors
Engineer/Engineer, Senior | DDR Subsystem, QCT
Qualcomm
San Diego, CA
02.2018 - 09.2022
- Led the development of Memory Controller architectural models for various LPDDR technologies (LP4, LP5, LP6).
- Conducted modeling and performance analysis of enhanced read-write algorithms for LP5.
- Mitigated performance impacts of additional pipelines to support increased LPDDR frequencies.
- Provided critical performance feedback for 4x refresh rate in automotive chips using LP4.
- Performed early performance evaluation of timing parameters essential for defining LP6 specifications.
Interim Engineering Intern | Memory NoC, QCT
Qualcomm
San Diego, CA
06.2016 - 08.2016
- Assisted in the functional verification of Memory NoC and associated bus protocols.
- Developed System Verilog assertions to validate the functional correctness of IP.
Education
Master of Science - Computer Engineering
Columbia University
New York, NY12-2017
B.Tech - Electronics And Communication
Vellore Institute of Technology
Vellore, India05-2016
Skills
- Micro-architectural modeling
- Performance analysis
- Cache and DDR architecture
- Benchmark performance analysis
- C/C, awk, python
Patents
P.Deshmukh, S.Thoziyo, V.Balakuntalam "Memory System with Adaptive Refresh"
- U.S Patent: US-12153531-B2
P.Deshmukh, S.Thoziyo, V.Balakuntalam "Multi-core Memory Controller"
- US Patent: US-12038855-B2
Timeline
Engineer, Staff | GPU Subsystem, QCT
Qualcomm
09.2022 - Current
Engineer/Engineer, Senior | DDR Subsystem, QCT
Qualcomm
02.2018 - 09.2022
Interim Engineering Intern | Memory NoC, QCT
Qualcomm
06.2016 - 08.2016
Master of Science - Computer Engineering
Columbia University
B.Tech - Electronics And Communication
Vellore Institute of Technology
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