Summary
Overview
Work History
Education
Skills
Timeline
Generic

WILLIAM D. REPKO

Gilbert,AZ

Summary

To be able to contribute to a Company's growth, development and goals which offers professional challenges utilizing interpersonal skills, excellent time management and problem-solving skills.

ADDITIONAL INFORMATION: Involved with ASIC Design for the past 26 years. Experienced in micro-architecture, RTL entry, synthesis, and validation. Also have experience in product development from initial concept through design and test. Many of those designs have seen silicon. Detail oriented with excellent technical documentation. Ability to maintain schedules. Strong with leadership, mentoring, decision-making, creative thinking, technical analysis and communication skills.

Overview

25
25
years of professional experience

Work History

Senior Design Engineer

NXP Semiconductor
Chandler, AZ
05.2013 - Current
  • Wrote analog behavioral models for integration into full chip verification environment for numerous products
  • Led a UVM verification team for a touch sensor chip
  • Defined, assigned and coordinated tasks to keep production schedule
  • Created initial verification environment
  • Wrote tests to guarantee functionality
  • Created verification environments and tests for numerous products such as LED controllers, USB power delivery, battery management, and security controllers.
  • Worked with architects and product designers to implement and debug new technology.
  • Coordinated technical requirements, scheduling and solution development for engineering design and test issues.

Senior Design Engineer

Intel Corporation
Chandler, AZ
06.2009 - 05.2013
  • Micro-Architected, designed, and implement bridge design for H264 encoder which was used for communication of high-speed video data to and from the encoder
  • Modified and integrated low speed serial I/O interfaces such as SPI, I2C, and GPIO for SOC chip
  • Micro-Architected, designed, and implemented a hardware mutual exclusivity block.
  • Interacted with project leaders and stakeholders to define requirements and generate and maintain design development documents.
  • Processed customer-supplied requirements into actionable design plans through critical thinking and independent research.

Senior Design Engineer

Freescale Semiconductor
Chandler, AZ
11.2007 - 06.2009
  • Designed and implemented changes for the Lynx 5 (SerDes)
  • Created validation environment and tests for the same
  • Conducted research of previous Lynx technical documentation for knowledge and understanding of the current design specifications.

Senior Design Engineer

Intellasys Corp
Tempe, AZ
02.2007 - 10.2007
  • Micro-Architected, designed, and validated SATA bridge logic for storage products
  • Acquired SATA knowledge, implementation, integrating with a core processor, creating new tests as well as modifying existing tests, and performing synthesis.

Senior Design Engineer

Intel Corporation
Chandler, AZ
01.2003 - 01.2007
  • Micro-Architected, designed, and validated PCI-Express logic for Communications products
  • Learned PCI Express specification, implementation of the transaction layer logic, integrating with 3rd party PHY/link
  • Modified existing tests and created new tests
  • Worked with the synthesis and layout teams to ensure quality silicon.

Senior Design Engineer

Corrent Corporation
Tempe, AZ
02.2001 - 07.2002
  • Micro-Architected, designed and validated multiple units for packet processing engine used in a data security processor
  • Researched specifications for the product
  • Developed a data flow, partitioned the design, implemented design using Verilog, simulated using Synopsis VCS, generated bus functional models for verification, produced and executed the test plan
  • The test plan was geared to achieve 100 percent code, conditional, branch and toggle coverage.

Component Design Engineer

Intel Corporation
Chandler, AZ
01.1996 - 02.2001
  • Micro-Architected, designed and validated ASIC PCI and Firmware Hub interfaces for data encryption/decryption devices
  • Required earning the PCI specifications, determining the data flow, partitioning the logic, implementing the logic using VHDL, simulating the design using Modelsim, generating bus functional models for validation, and generating and implementing a test plan
  • The test plan was geared to achieve 100 percent code, conditional, branch and toggle coverage
  • Micro-Architected, designed and validated ASIC PCIX master interface for first generation Infiniband product
  • This necessitated learning the Infiniband specification, developing the data flow, partitioning the design for meeting timing requirements, implementing the logic using VHDL, simulation the design using Modelsim, generating bus functional models for verification, and generating and implementing the test plan
  • Created tools for aid in design and pre-silicon validation of ASIC devices
  • These tools aided in the automatic creation of individual units for the design as well as simplified running of the tests in the Modelsim environment
  • Performed silicon debug using IMS tester
  • This involved generating the schematic for the tester head, generating patterns for the tester, and debugging the actual silicon on the tester.

Education

B.S - Computer Engineering

Auburn University
Auburn, AL

Skills

    ASIC design flow

    Performed gate level simulation

    Ran synthesis using Synopsys

    Full chip simulation

Timeline

Senior Design Engineer

NXP Semiconductor
05.2013 - Current

Senior Design Engineer

Intel Corporation
06.2009 - 05.2013

Senior Design Engineer

Freescale Semiconductor
11.2007 - 06.2009

Senior Design Engineer

Intellasys Corp
02.2007 - 10.2007

Senior Design Engineer

Intel Corporation
01.2003 - 01.2007

Senior Design Engineer

Corrent Corporation
02.2001 - 07.2002

Component Design Engineer

Intel Corporation
01.1996 - 02.2001

B.S - Computer Engineering

Auburn University

Similar Profiles

CREATE PROFILE
WILLIAM D. REPKO