Wonbin Seo

Electrical and Computer Engineering M.S. student specializing in RTL design, FPGA acceleration, and VLSI digital systems. Hands-on experience designing ALU and MAC architectures using Synopsys EDA tools and implementing a full 8-bit microprocessor in Cadence Virtuoso. Seeking entry-level roles in RTL/ASIC or FPGA design.

RTL Design of MAC Units | Verilog, Synopsys EDA tool

• Implemented parameterized ALU and MAC architectures with synthesizable RTL
• Validated functional correctness and synthesis readiness using RTL simulation and Synopsys EDA tools
• Analyzed area–timing trade-offs to inform datapath and control structure decisions

8-bit Microprocessor VLSI Design | Candence Virtuoso

• Designed a complete 8-bit microprocessor datapath and control logic at the transistor level
• Implemented full-custom schematics and layouts using Cadence Virtuoso following VLSI design rules
• Verified physical design correctness through schematic-driven layout workflows (DRC/LVS)

Section Leader — 65th Medical Brigade, 8th U.S. Army | Camp Humphreys, South Korea
Feb 2018 – Oct 2019

• Led and trained personnel responsible for maintaining secure IT and computing systems
• Resolved hardware and software issues under time-critical operational constraints

Food Bank Staff — Michigan State University | East Lansing, MI
Sep 2025 – Dec 2025

• Supported campus food distribution operations and inventory management