Xhino Domi
Hillsboro,OR
Summary
Proven System Debug and Validation Engineer at Intel Corporations, adept in Python and technical reporting, enhanced system debug efficiency and mentored junior engineers. Spearheaded validation plans for cutting-edge projects, leveraging root cause analysis and troubleshooting skills to significantly improve operational risk management and system reliability. Detail-oriented, organized, and meticulous employee. Works at fast pace to meet tight deadlines. Enthusiastic team player ready to contribute to company success.
Overview
6
6
years of professional experience
Work History
System Debug Engineer
Intel Corporations
06.2022 - Current
- Established strong working relationships with designers and architects, fostering trust and collaboration to solve and debug problems.
- Developed positive working relationships with leads across validations teams to effectively coordinate work activities and develop more comprehensive test plans.
- Collaborated with Pre-Si teams and helped worked on their tests and debug to accelerate the health of the silicon before Tape-In.
- Supported junior engineers through mentorship, offering guidance on complex problem-solving and technical skills development.
- Established working methodology and process of debugging within the team to better enhance debug time and efforts.
- Created multiple scripts to properly debug issues and simplify the complexity of the system or hardware interfaces.
- Lead debug initiatives to close on complex debugs or difficult to reproduce issues
System Validation Engineer
Intel Corporations
06.2018 - 06.2022
- Mentored junior engineers in best practices for validation engineering methodologies improving team skillsets.
- Established strong working relationships with multiple validation teams and FW teams.
- Conducted root cause analysis on deviations during validation activities, enabling timely resolution of technical issues.
- Reduced operational risks associated with validated systems through review process and constant research around the specifications, hardware design, and firmware development,
- Generated validation plans for 10th Gen, 12th Gen, and Ultra 100 series projects targeting Idle Power Management system level features.
- Validated SoC level Power Management features, primarily focused on Idle Power Management, from end-to-end HW, FW, SW stack.
Education
Bachelor of Science - Computer Engineering
Florida Polytechnic University
Lakeland, FL05.2018
Skills
- Technical reporting
- System Troubleshooting
- Root Cause Analysis
- Assembly (MIPS & x86)
- C/C
- Python
- Verilog/VHDL/System Verilog
- Verdi
Languages
Spanish
Native or Bilingual
Timeline
System Debug Engineer
Intel Corporations
06.2022 - Current
System Validation Engineer
Intel Corporations
06.2018 - 06.2022
Bachelor of Science - Computer Engineering
Florida Polytechnic University
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