Xiaoyang Liu
San Jose,CA
Summary
Principal Software Engineer with strong expertise in low-level C development, hardware bring-up, and embedded systems debug. Experienced in DisplayPort and PCIe protocols, with deep knowledge of register programming, state machine analysis, and initialization sequences. Proven track record of debugging complex hardware/software interactions, collaborating across hardware, firmware, and driver teams to enable reliable SoC bring-up and optimization.
Overview
7
7
years of professional experience
Work History
Principal Software Engineer
Cadence Design Systems
San Jose
02.2019 - Current
- Developed Verification IP (VIP) for the DisplayPort protocol in C, enabling design verification teams to validate compliance and integration of SoCs.
- Modeled register-level behavior, link training sequences, and AUX channel transactions, providing realistic environments for firmware and driver teams to test bring-up flows.
- Worked closely with customer hardware teams to debug complex issues during DUT integration, analyzing trace logs, register dumps, and state machine stalls.
- Identified and helped resolve a wide range of issues, including customer configuration errors, DUT design bugs, and VIP usage problems, ensuring faster debug cycles, and improved bring-up success rates.
- Delivered customized VIP solutions based on customer-defined specifications, adapting register models, state machines, and protocol features to meet unique SoC verification requirements.
- Implemented error injection and negative test scenarios, creating controlled protocol violations and timing errors to validate the DUT's error handling and robustness.
- Secondary: contributed to PCIe VIP development and debugging, applying similar register/state machine modeling, and customer support practices.
Education
Master's degree - Computer Engineering
University of Southern California
Los Angeles, CA05.2019
Bachelor's degree - Electrical Engineering
University of Electronic Science And Technology of China
Chengdu, China06.2017
Skills
- C/C
- Python
- UVM methodology
- DisplayPort Protocol
- PCIe Protocol
Timeline
Principal Software Engineer
Cadence Design Systems
02.2019 - Current
Master's degree - Computer Engineering
University of Southern California
Bachelor's degree - Electrical Engineering
University of Electronic Science And Technology of China
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