Yazdan Torabian-Esfahani

Seeking a dynamic position in: Digital Logic Design targeted towards FPGA Design in System Oriented Companies with Verilog, System Verilog and VHDL as RTL designer. Also has experience and capability in UVM. Senior FPGA Design Engineer offering 24 years of experience in FPGA design engineering Expertise in a Nutshell: FPGA design with Verilog/VHDL (RTL) and ability to generate testbenches with Verilog/VHDL and UVM. understanding of Serdes PCS, Comma detection and alignment, 8b/10b decoder, LFSR scrambler .Deep understanding of AXI bus protocol, Synopsys DW I2C APB . Deep understanding of Signal processing concepts such as : FIR filters, FFT, z-plane , FIR poly phase filters for sampling rate conversion, DDS and Cordic, De-emphasis, equalization. Deep understanding and Signal Analysis of Synopsys PCI Express Design IP. Deep understanding of High speed Serdes Architecture, PCI Express , SAS ,SATA, USB 3.0 , Aurora Protocol. Implementation of Aurora protocol in Verilog and VHDL Interesting Home Project: Design of a Deskew Circuit (Channel bonding) with Verilog (RTL) for DeSkewing a X4 Lane . Design uses: serializer, de-serializer, Crossing Clock domain Fifo, Comma Detection Align, Sort Algorithm for finding the deskew Description of UVM Projects: Design of UVM Force agent for changing the trigger threshold of a comparator for Lecroy in 2010-2011 Design of UVM full testbench for RTX for Verification of RF FPGA that was responsible to interact with the main FPGA of the system through custom serial interface and implements of ADC gating functions. 2024