Summary
Overview
Work History
Education
Skills
Accomplishments
Timeline
Generic

Yunkun Lin

LOS ANGELES,CA

Summary

Motivated and enthusiastic EE PhD student seeking a challenging summer internship opportunity to gain hands-on experience and contribute to design and test. With a strong academic background and a passion for design and DFT area, I am eager to apply my knowledge and learn from industry professionals.

Overview

4
4
years of professional experience

Work History

PhD Student

Sandeep Gupta
LOS ANGELES, CA
08.2021 - Current
  • Research in Aging and Process variation for logic part in pipeline CPU and Memory part, aim to build predictive and present-state testing methods for aging+ in Logic part and memory part, including DFT for predictive testing, new tests patterns, and BIST implementations
  • Research in Memory Testing, aim to build ATPG to generate all march tests target for certain types of faults and extend them to get march tests targeting for certain fault series with fast speed and optimal proof according to proven constrains or get the largest fault coverage with the limitation of test length in realistic memory test.
  • Research in Design for testability (DFT) for RSFQ circuits, aim to Build complete system for RSFQ circuits which enable scan chain to shift in test parameters and shift out the corresponding test response in different time domain and build special test and timing control system which satisfy requirements of RSFQ logic
  • Research in metastability of a Single Flux Quantum DFF, aim to derived an analytical model for metastability in DFF-based SFQ synchronizers

Master Student

USC
Los Angeles, CA
08.2019 - 12.2020
  • Implement of DFT for given CMOS circuit, aim to implement of ATPG using D algorithm and podem algorithm, random pattern generation to test circuit , parallel fault simulation and deductive fault simulation
  • Design of Josephson Junction Based Superconducting Cache
  • Design of a Network on chip (NOC) with 5-stages Pipelined CPU in each cores
  • Implement of tomasulo algorithm, CMP, PCIE and GPGPU
  • Design of Digital Phase Locked-loop (DPLL)

Education

Bachelor of Science - Physics

University of Science And Technology of China
China
06-2019

Ph.D. - Electrical Engineering

University of Southern California
Los Angeles, CA

Master of Science - Electrical Engineering

University of Southern California
Los Angeles, CA
12-2020

Skills

Python/ Verilog/ C/ C/ MATLAB/ VHDL/ Cadence/ Synopsys/ Xilinx/ Mathematics/ Origin/ Latex/ CAD

Accomplishments

MS Honors program, USC 2020

Bronze Award for Outstanding Student Scholarship, USTC 2018

Bronze Award for Outstanding Student Scholarship, USTC 2017

Silver Award for Outstanding Student Scholarship, USTC 2016

Timeline

PhD Student

Sandeep Gupta
08.2021 - Current

Master Student

USC
08.2019 - 12.2020

Bachelor of Science - Physics

University of Science And Technology of China

Ph.D. - Electrical Engineering

University of Southern California

Master of Science - Electrical Engineering

University of Southern California
Yunkun Lin