Anirudh Kumar

Design and Layout of a 14-bit SAR ADC using 14 nm Global Foundries FINFET Cadence Virtuoso at 40 MHZ bandwidth in Prof Sudhakar Pamarti's UCLA SPACE research group. This ADC reduces power consumption from 9 to 5 milliwatts and samples more bits per second at 0.35 GHz clock frequency compared to El Shater’s ISSCC work.

• Simulating in Cadence a 5.2 GHz DC receiver using a voltage-controlled oscillator, LNA, and two mixers to maintain an IIP3 of -15 dBm, Receiver gain > 30 dB, phase noise of LO < -100

• Tape out of 2.4 GHz PLL (Simulation, Layout in Cadence Skywater 130 nm, PCB Design in Altium)

• Implemented an Equifilling Program allocation algorithm using minimum area and power, and 8 clock cycles of signal processing latency using Verilog, and Synopsys.

• Designed a fully differential wide-band op-amp intended for use in a switched-capacitor low-pass filter using Cadence.

• Design a broadband amplifier in ADS (single-stage or multi-stage) which is matched to 50ohm source and load using 4 parallel amplifiers and a 4:1 Wilkinson power combiner

• Design a 3.6 GHz RF Power Amplifier in ADS using a coupler and coaxial lines (microstrips)

• Ran Level 1 ET, APT, mismatch, ruggedness, coex, desense, DC leakage, RF leakage for duplexer boards for LNA, PA, ASM using spectrum analyzers, load pull tuners, couplers, signal generators

• Plotting small signal parameters, create compliance matrices, and generating backfills of test results in ADS, PAT

Used VNA, spectrum analyzers, signal generators , and Smith Chart for RF measurement

Metrics Validation for Automated Vehicle Operational Safety - Designed a controller to store vehicle speed, lateral or longitudinal control, headway speed at intersections from different traffic scenarios

Create intersection scenarios to test the reliability of autonomous vehicles using LIDAR sensor data in a simulator called CARLA