Summary
Overview
Work History
Education
Skills
Publications
Continuing Education
Timeline
Generic

Bruce Kochheiser

Driftwood,Tx

Summary

Passionate about delving into the intricacies of failure analysis, seeking an FIB/SEM Failure Analysis Engineering position focused on Sub-micron CMOS Devices. With a strong background in this field, confident in the ability to make valuable contributions and enhance the organization's success. Eager to contribute skills and drive continuous improvement, dedicated to utilizing expertise to effectively analyze and resolve complex issues, ensuring optimal performance and reliability.

Overview

41
41
years of professional experience

Work History

Sr Device Engineer Technician

NXP Semiconductors
05.2002 - Current
  • Working with Hamamatsu 1000 OBIRCh (Optical beam induced resistance change) to identify both high resistive locations as well as shorts
  • Hitachi SEM’S 4800, 8100 close inspection of failures and measured thicknesses of processed layers
  • Worked with FIBS 820,830,835, Strata, and Helios
  • Worked directly with Eng
  • To develop and find single Bit failures on Hip7, Hip8, SOI using Knights/Camelot/Avalon CAD navigation software to overlay the device schematic to the FIB (Focused Ion Beam)
  • And precisely cut the bit cell to find root causes, as to which layer the single bit failure had occurred
  • Helped develop methods used for Logic mapping Procedures on M14E LTE2, L93S LTE, M68C Copperhead, now M39E Draco
  • I was successful in finding the first logicmap/Scan Fa hotspot failure on 18 die on L93S Neptune LTE
  • These 18 locations were feed into FabSolve which created a KLARF file from the SEMVision G3 setup to map across wafers on other L93S lots at metal 1 ACI
  • Tool owner of the Trion Dry oxide etcher, creating recipes for Nitride removal, as well as other oxide recipes

Lab Technician

Motorola Semiconductor
07.1995 - Current
  • Maintained documentation on tests performed in lab.
  • Maintained a safe and organized laboratory environment, adhering to strict safety protocols.
  • Maintained safe, tidy and organized laboratory environment for accurate test results.
  • Conducted routine quality control checks to ensure accurate test results and maintain laboratory standards.
  • Trained new laboratory personnel to apply proper laboratory techniques and best practices.
  • Worked on Wafer requests to produce the best results using both the FIB Focused Ion Beam, and the SEM Scanning Electron Microscope to capture the AOI Area of interest using a digital capturing system.
  • Capable of deprocessing wafer samples using Buhler polishing wheels with colloidal .5 um solution.

Sr Failure Analysis Device Engineer Technician

Motorola
05.2002 - 04.2025

Working with Hamamatsu 1000 OBIRCh (Optical beam induced resistance change) to identify both high resistive locations as well as shorts. Hitachi SEM’S 4800, 8100 close inspection of failures and measured thicknesses of processed layers. Worked with FIBS 820,830,835, Strata, and Helios. Workeddirectly with Eng. to develop and find single Bit failures on Hip7, Hip8, SOI using Knights/Camelot/Avalon CAD navigation software to overlay the device schematic to the FIB (Focused Ion Beam). And precisely cut the bit cell to find root causes, as to which layer the single bit failure had occurred. Helped develop methods used for Logic mapping Procedures on M14E LTE2, L93S LTE, M68C Copperhead, now M39E Draco. I was successful in finding the first logicmap/Scan Fa hotspot failure on 18 die on L93S Neptune LTE. These 18 locations were feed into FabSolve which created a KLARF file from the SEMVision G3 setup to map across wafers on other L93S lots at metal 1 ACI. Tool owner of the Trion Dry oxide etcher, creating recipes for Nitride removal, as well as other oxide recipes.

03.2000 - 05.2002
  • Working on HiP6W K17N, K45N and Critical Design Rules (CDR) Products
  • Part owner of K74D, KO8X, and K85C
  • Worked with Eng
  • Supporting product transfer of J27C to MOS-11
  • Strong analytical, and problem solving techniques, that were helpful in communicating new processes
  • Heavily involved with a cross-functional team, lending knowledge and experience when needed
  • Finding ways to increase yields, and increase the throughput
  • Worked with process Eng
  • To convert all resists to one standard, from I120, to UV210 resist (CAB approved)
  • Mentored others when asked, or lended advice on previous related experiences
  • Documented all new processes and developed activities appropriately
  • Ensured projects were completed on time (OSIR) format
  • Working with software to find and correct problems as they may arise
  • EDAS used to extract data, then manipulating data in JUMP 4.0 software where Charts and graphs are generated and commonalty’s to find and implement fixes on tool excursions
  • Worked directly with Eng
  • To develop and find single Bit failures using Knights CAD navigation software to overlay the device schematic to the FIB (Focused Ion Beam)
  • And precisely cut the bit cell and find root causes, and to which layer the single bit failure had occurred

Sr. Device Lab Technician

Motorola
07.1995 - 03.2000
  • Worked in the MOS13 Device lab reporting on root cause/s of failures on wafer runs with zero yields, and help implement corrective actions, improving and enhancing yields
  • Training select personnel on all lab equipment (i.e
  • SEM, FIB, TXRF, FIBing TEM samples, Polishers, RIE etchers, Light microscopes, EDX, and Wet hoods)
  • Qualify all new devices that are introduced to the production lines
  • Work on customer returns to help identify causes/effects as to their failures
  • Work on sustaining the fab as required with tool quals, and matrix’s that are required by the Reps
  • Working with packaged parts, and full flow wafers, deprocessing to Find particles, as well as other defects that attribute to failing die, or wafers
  • Projects included: (1) Working in conjunction with all production and yield engineering on process, fine tuning, and DOE`s (Design of Experiments)
  • (2) Interfacing with the analytical needs on the problems that arise in production and in the field
  • (3) Maintain and oversee all lab operations and upkeep-PM`s of all the Tool sets
  • Work with Product engineering on root causes of device failure of customer return parts

Analytical Lab Technician I QA

Sony Microelectronics
06.1991 - 07.1995
  • Worked in the analytical lab group QA improving and enhancing semiconductors design, process, and yields
  • Training select personnel on all lab equipment
  • Principle responsibility: Programmable Array Logic (PAL) 22v10's High Speed Bipolar Devices, EPD's, SLIC's, High Speed CMOS SRAM, ASIC, and SONIC Devices
  • Daily duties include: (1) Determining root cause device failure at wafer sort on products below forecast for both Bipolar and CMOS technologies
  • (2) Improvement of device quality, reliability, performance and yields
  • (3) Reports on root cause failure analysis on wafer runs with zero yields and implement corrective action
  • (4) Work with the Sony Design Center on debugging and correcting new devices for production
  • (5) Qualify all new devices that are introduced to the production lines
  • (6) Work on customer returns for Sony America
  • (7) Helped Implement outside sales of analytical services to Southwest Research Institute, UTHSC, Texas Research Park, Wilford Hall Hospital, BAMC, Kelly, Bryant Lee and Assoc
  • Projects included: (1) Working in conjunction with all production and yield engineering on process, fine tuning, and DOE`s
  • (2) Interfacing with the analytical needs on the problems that arise in production and in the field
  • (3) Maintain and oversee all lab operations
  • (4) Work with Product engineering on root cause device failure’s of customer return chips and implement fab corrections
  • (5) Implement and service all outside evaluations in the Materials and Bio Medical community
  • Equipment used on a daily basis to characterize products and help maintain yields are; JEOL 6400FEC SEM, Amray 1645 SEM with Noran 5500 Vista EDS system, SEIKO 8100 FIB, FEI FIB 611, ZEISS LSM with OBIC, ZEISS, Olympus, and Poly-Var optical microscopes, Cleaving, polishing, and acid staining, wet and dry etching, and knowledge of semiconductor devices physics are exercised regularly

FAB operator (specialist)

04.1984 - 06.1991
  • FAB operator (specialist) in all areas of the process such as photo masking, etch group, epi, implant, diffusion, metals, glass deposition, backgrind, polish, gold

Education

Bachelor of Business Management -

St Edwards University
Austin, Texas
01.2015

Assoc. of Science Degree -

Palo Alto College
San Antonio, Texas
01.1995

Skills

  • Microchip FIB Location Mapping using Knights/Avalon software
  • Utilizing OBIRCh (Optical Beam Induced Resistance Change)
  • 4800, and 8100 Hitachi SEMs to capture images of the layer interested in
  • Utilizing the FIB (Focused Ion Beam) 835, Strata, and the Helios to cut the samples with precision
  • Using the OXFORD EDS System which helps to identify elements within the samples/particles with is attached to the SEM

Publications

  • Material Analysis Lab Brochure; for outside sales of Sony Analytical Services.
  • Effect of Surface Roughness of Titanium Implants on the Proliferation and Differentiation of Human Osteoblast-like Cells (MG63) - Published in the Journal of Biomedical Materials Research.
  • Evaluation of Focused Ion-Beam cross Sectioning of Resin-Dentin Interfaces - Texas Society for Electron Microscopy and Dental Materials Journal.
  • Effects of Titanium Surface Characteristics on Chondrocytes and Osteoblasts in Vitro - Published in the Journal of Biomedical Materials Research.
  • Specific Site Cross Sectional Sample Preparation Using Focused Ion Beam for Transmission Electron Microscopy Characterization - Published in the Journal of Progress in Crystal Growth and Characterization of Materials Vol. 36 1998 and 1997 Motorola Winter AMT Symposium.

Continuing Education

  • SPC - Statistical Process Control, 06/90
  • JEOL - JSM 6000F Series (Field Emission) SEM Operations Training Course, 04/92
  • CMOS Process Flow by Kiyoshi Mori, 02/94
  • Materials Engineering Institute ASM - Principles of Failure Analysis, 03/94
  • Kepner Tregoe - Problem Solving & Decision Making, 04/94
  • Lehigh University - Micro characterization of Electronic Materials, Devices and Packages, 06/94
  • Mechanical Universe Caltech Physics video library seminar, 08/94
  • World of Chemistry. Failure and Yield Analysis Seminar, 02/95
  • Device Physics - Motorola Univ, 09/96
  • MOS 171 CMOS Circuit Design - Motorola Univ, 04/97
  • Unix 101 - Motorola Univ, 05/97
  • Utilizing the Six Steps to Six Sigma - Motorola Univ, 05/98

Timeline

Sr Failure Analysis Device Engineer Technician

Motorola
05.2002 - 04.2025

Sr Device Engineer Technician

NXP Semiconductors
05.2002 - Current

03.2000 - 05.2002

Lab Technician

Motorola Semiconductor
07.1995 - Current

Sr. Device Lab Technician

Motorola
07.1995 - 03.2000

Analytical Lab Technician I QA

Sony Microelectronics
06.1991 - 07.1995

FAB operator (specialist)

04.1984 - 06.1991

Assoc. of Science Degree -

Palo Alto College

Bachelor of Business Management -

St Edwards University
Bruce Kochheiser