Summary
Overview
Work History
Education
Skills
Toolsknowledge
Personal Information
Certification
Timeline
Generic

Ching-lung Cheng

Fremont,CA

Summary

Highly skilled Physical Design Engineer specializing in digital design and system-on-chip (SoC) projects. Proficient in problem-solving, data analysis, ASIC design flow, EDA tools, and collaborating effectively in cross-functional teams. Demonstrated success in tape-out across various technologies.

Overview

23
23
years of professional experience
1
1
Certification

Work History

Physical Design Engineer/SoC APR lead; Engineering manager

Intel
08.2013 - Current
  • 2017-present: Manage a team of 5-7 members; responsible for task assignments, mentorship/coaching, and performance evaluations.
  • Sep 2023-present: APR lead and physical design engineer in the latest Xeon SoC, owned different partitions through different milestones.
  • Dec 2019-Oct 2023: APR led to coordinate 7nm DDR subfc/subsystem physical design and successfully delivered subsystem for Xeon SoC product tape-out.
  • 2018-2019: led a major 10nm Subfc/subsystems and coordinated SoC physical design activities, including high bandwidth planning in server SoC during early milestones.
  • 2017-2018: Physical design engineer and lead to coordinate physical design activities for 14nm chipset product and achieved successful tape-out. Worked with different process owners. Owned major internal fabric partition.
  • 2015-2016: Physical design engineer for 14nm audio subsystem. Owned a specific host partition and guided interface timing in the subsystem. Developed a custom clock tree to address long/short clock tree issues between different partitions in the subsystem. Provided guidance to the partition with an L shape to prevent congestion.
  • 2013-2014: Physical design engineer for 14nm High Speed DDR PHY digital data module; provided fixes for UPF issues; co-worked with RTL designer on critical timing paths; supported other partition owners; created own interface timing constraints; and implemented design with DCG/ICC (early physical synthesis); built small custom tree to control the high-speed flops.
  • 2013: Physical design engineer for 22nm DDR interface PHY timing methodology improvement, in-timing analysis with DMSA, and timing ECOs.

Senior Engineer

TSMC North America
04.2011 - 08.2013
  • Hardened 40nm/28nm ARM A9 core with dual core or quad core bottom-up implementation. Involved in early 20nm ARM core with specific PPA requirements for testchip to help evaluate routing pattern rules challenges.
  • Evaluated different EDA tools for implementation, such as Cadence Azuro clock data optimization methodology, Synopsys Dorado Tweaker ECO, against PTECO for TSMC TFM reference flow improvements.

Senior Engineer

Kawasaki Microelectronics America (MegaChips)
05.2001 - 04.2011
  • Started as a Front-End Engineer, collaborating with customers by providing feedback after synthesis. Created pin/ball assignments following package design rules. Handled ATPG processes, including scan, JTAG, and BIST, with internal flows. Worked with Backend to close timing by providing ECOs. Worked with a Test Engineer to debug test failures.
  • From 2006 onwards, I worked as a physical design engineer in the backend domain - from RTL synthesis or netlist to GDS out, in multiple consumer/networking ASIC designs in 65nm, 90nm, and 130nm.

Education

MSEE -

University of Southern California
01.2001

BSEE -

University of Southern California
01.1999

Skills

  • Extensive physical design experiences from RTL to GDS out
  • SoC physical design / planning
  • Partition level placement , routing analysis , convergence
  • Clock Structures, Clock tree synthesis, debug
  • VCLP multiple power domain issues
  • Timing convergence
  • Power optimization
  • PGEM / IR optimization / prevention
  • 7nm DDR subfc/subsystem physical design
  • 10nm Subfc/subsystems physical design
  • 14nm chipset physical design
  • 22nm DDR interface PHY timing methodology improvement
  • ARM core implementation
  • EDA tools evaluation
  • Team leadership/ Task assignments / Planning
  • Mentorship/coaching/Performance evaluations

Toolsknowledge

  • Proficient knowledge of Awk and Tcl; Synopsys Fusion Compiler, Primetime; Conformal LEC; (Redhawk, Tweaker, Formality) ; Leveraging ChatGPT to improve scripting skills.
  • ASIC flow and methodology from RTL to GDS.

Personal Information

Status: US Citizen

Certification

  • Project Management Professional (PMP) - Project Management Institute.

Timeline

Physical Design Engineer/SoC APR lead; Engineering manager

Intel
08.2013 - Current

Senior Engineer

TSMC North America
04.2011 - 08.2013

Senior Engineer

Kawasaki Microelectronics America (MegaChips)
05.2001 - 04.2011

MSEE -

University of Southern California

BSEE -

University of Southern California

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Ching-lung Cheng