Work Preference
Summary
Overview
Work History
Education
Skills
Extracurricular Activities
Languages
Timeline
StoreManager
Divyanshee Mertiya
Open To Work

Divyanshee Mertiya

Work Preference

Work Type

Full Time

Location Preference

HybridRemote

Important To Me

Work-life balanceFlexible work hoursCareer advancementCompany Culture

Summary

Accomplished Staff Mask Designer at SanDisk with expertise in layout optimization and quality assurance. Proven track record in leading teams to achieve timing closure and enhance design performance. Adept at multi-tasking and mentoring, driving project success while maintaining high standards in physical verification and risk assessment.

Overview

9
9
years of professional experience

Work History

Staff Mask Designer

SanDisk
Bengaluru
03.2024 - Current
  • Oversaw large partitions in full chip from concept study to tape-out, ensuring project continuity.
  • Conducted thorough design reviews to uphold quality standards and timeline adherence.
  • Managed simultaneous activities while meeting strict deadlines consistently.
  • Documented design processes meticulously, maintaining accurate project records throughout.
  • Optimized layout designs to enhance performance and minimize area usage effectively.
  • Mentored team members, delivering guidance on best practices and technical techniques.
  • Addressed iteration challenges by training new members without delaying project timelines.
  • Additionally, gained experience in physical design implementation by executing PnR on a digital block with Synopsys ICC2

Sr. Mask Designer

Western Digital
Bengaluru
03.2021 - 02.2024
  • Led high-speed block development with TM1200, TM2400, and TM3600 across various technologies.
  • Improved layouts by applying insights gained from previous projects.
  • Conducted research on solutions to speed issues in Data Path blocks using Foot Switch, acquiring trade secrets for enhancements.
  • Enabled standard cell library integration with FSW for future projects.
  • Executed power planning and performed Totem Early Analysis to address IR drop hotspots during layout development.
  • Managed complete partition, overseeing all pre-Si checks to enhance layout quality with diverse tools.
  • Directed a small team, ensuring adherence to timelines and accuracy.
  • Achieved timing closure while meeting all design specifications.

Mask Designer

Western Digital
Bengaluru
06.2018 - 02.2021
  • Led layout design for high-performance analog and mixed-signal circuits, including temperature sensors and voltage generators.
  • Collaborated with design and verification teams to meet all design specifications.
  • Conducted DRC, LVS, and quality checks, resolving issues to meet tape-out deadlines.
  • Reduced layout turnaround time by optimizing design methodologies.
  • Integrated full-chip level using VB-TAP areas.
  • Executed full-chip LVS/DRC and other verification checks.
  • Addressed EMIR, antenna, and latchup issues effectively.
  • Utilized Module Router for digital blocks to enhance efficiency.

Contractor

JGDTech Pvt. Ltd.| Randstad
Bengaluru
02.2017 - 05.2018
  • Developed STD cell libs with dense placement, and routing to obtain min. area on a tight schedule.
  • Performed various quality checks.
  • Created layouts of Macros & custom blocks like Voltage Regulator, Decoder, Opamps, etc. using cadence virtuoso.
  • Fulfilling design requirements by adhering to the signal list and optimizing area, physical verification, and quality checks were done using various tools.
  • Responsible for integration at the next level and power plan.
  • Worked on TEG projects for future technologies.

Intern | PG Diploma in Full Custom

RV-VLSI
Bengaluru
07.2016 - 01.2017
  • Created layouts of combinational as well sequential circuits in 90 nm technology with minimum possible parasitics and optimized area in less than given time using Synopsis ICV.
  • Responsible for Physical verification checks - DRC & LVS using Caliber.
  • Built SRAM from scratch using min area and verified DRC & LVS.
  • Worked on various nodes - 180nm, 90nm, 28nm.
  • Gained knowledge of PD flow, STA, Synthesis, Extraction, etc.

Education

M.TECH. - MICROELECTRONIC

Birla Institute of Technology & Science
Pilani
01.2023

B.TECH. - ELECTRONIC AND COMMUNICATION

Poornima Institute of Engineering & Technology
Jaipur
01.2016

PUC / 12TH -

Sahara Public Sr. Sec. School
Kota
01.2012

SSLC -

Saint Meera Sr. Sec. School
Sheoganj, Sirohi
01.2010

Skills

  • Collaborative teamwork
  • Mentorship skills
  • Physical verification
  • Quality assurance
  • Team leadership
  • Layout optimization
  • Power planning
  • Adaptability
  • Multi-tasking
  • Agile
  • Quick Learner
  • Hard Working
  • Risk assessment
  • Problem solving
  • Critical thinking

Extracurricular Activities

  • Successfully organized multiple social events for the Western Digital Layout Team.
  • Led the planning and execution of Leadership Meets for large audiences, and managed two major annual company events—Jathre and the Western Digital Olympics.
  • Volunteered at the IOT-Next technical exhibition conducted by IESA, Bengaluru, and attended workshops on Critical Thinking, High-Impact Communication, and High-Impact Presentation Skills.
  • Contributed to the internal quarterly magazine as part of the editorial team and actively participated as a member of the Toastmasters Club.

Languages

  • Hindi
  • English

Timeline

Staff Mask Designer

SanDisk
03.2024 - Current

Sr. Mask Designer

Western Digital
03.2021 - 02.2024

Mask Designer

Western Digital
06.2018 - 02.2021

Contractor

JGDTech Pvt. Ltd.| Randstad
02.2017 - 05.2018

Intern | PG Diploma in Full Custom

RV-VLSI
07.2016 - 01.2017

M.TECH. - MICROELECTRONIC

Birla Institute of Technology & Science

B.TECH. - ELECTRONIC AND COMMUNICATION

Poornima Institute of Engineering & Technology

PUC / 12TH -

Sahara Public Sr. Sec. School

SSLC -

Saint Meera Sr. Sec. School
Divyanshee Mertiya