Duc Nguyen
Portland,OR
Summary
Looking for Senior Physical Design Engineer or Design Automation Engineer with deep experience from RTL to GDSII.
Overview
32
32
years of professional experience
Work History
Senior Physical Design Engineer
Avnera Corporation
Beaverton, Oregon
08.2008 - 10.2026
- Facilitated placement and routing for all digital blocks, ensuring optimal performance.
- Used extraction tool to create SPEF files for all corners.
- Validated timing closure across all modes and corners to meet design specifications.
- Executed layout verification by running DRC, LVS, and ANT checks to ensure compliance with design rules.
Automation Design Engineer
Intel
Hillsboro, Oregon
05.2006 - 08.2008
- Developed automated RTL-to-GDSII flow, enhancing design efficiency for Intel projects.
- Managed several digital blocks, executing place-and-route and resolving timing issues to meet project deadlines.
- Designed automation systems for Intel semiconductor manufacturing equipment
- Developed PLC logic for Intel production lines
- Integrated robotics into Intel fab automation projects
Senior Physical Design Engineer
Mobilian Corporation
Beaverton, Oregon
04.2001 - 05.2006
- Developed Mobilian wireless chip floorplans for physical design flow.
- Performed Place and Route and Layout verification for all digital blocks.
- Implemented scripts to extract parasitic information from layout and running static timing analysis.
Place and Route Application Engineer
Intel Corporation
Hillsboro, Oregon
01.1995 - 04.2001
- Supported place and route tool implementation across all projects, ensuring optimal performance.
- Evaluated new version releases for place and route tools, identifying key enhancements and potential issues.
- Created place and route technical documentation for project use.
- Provided ongoing support for applications in production environment, addressing user needs and troubleshooting problems.
- Delivered training and guidance on application software tools across all projects.
Education
Bachelor of Science - Electrical Engineering
University of Washington
Seattle, WA06-1994
Skills
- Floorplanning and pin optimization
- iOS macro and memories placement
- RTL to GDSII conversion
- Parasitic extraction
- Static timing analysis
- Timing closure strategies
- Pre and post-mask ECO implementation
- EMIR and signal integrity
- Signal integrity and DFM
- DRC, LVS, and antenna checks
- EDA tools: Innovus, Quantus, Tempus, Voltus, and Calibre
- Problem solving skills
- Programming languages: TCL, Python, Perl, Unix, C
Timeline
Senior Physical Design Engineer
Avnera Corporation
08.2008 - 10.2026
Automation Design Engineer
Intel
05.2006 - 08.2008
Senior Physical Design Engineer
Mobilian Corporation
04.2001 - 05.2006
Place and Route Application Engineer
Intel Corporation
01.1995 - 04.2001
Bachelor of Science - Electrical Engineering
University of Washington