Gururaj Siddaiah

ASIC and SOC Design Verification R&D Engineer with extensive experience planning, developing and implementing design verification for complex SOC designs for Mobile Baseband, WLAN, Touch, GPS SOCs and other ASICs.

• Executed verification cycles on a variety of digital designs, ranging from small blocks to large SoC's.
• Developed test plans and strategies for verifying design integrity of integrated circuits.
• Analyzed and debugged complex RTL code using simulation tools such as NCSIM, XCelium,VCS etc.
• Created assertions to check different properties at RTL level during simulation runs.
• Implemented directed tests and constrained random tests using SystemVerilog language constructs.
• Utilized UVM methodology for building verification environment components like drivers, monitors,scoreboards etc.
• Collaborated closely with designers to identify bugs early in the development cycle through debugging techniques such as waveform viewing or logic analyzers.
• Maintained detailed documentation of tasks completed throughout the entire design verification process.
• Participated actively in cross-functional meetings with Designers and Architects providing feedback on design decisions.
• Contributed towards improving existing processes around regression setup and execution which resulted in faster time-to-market delivery.
• Worked with cross-functional teams to achieve goals.