Akshay Mittal
Walnut Creek,CA
Summary
Creative and innovative prospect determined to bring ideas to life through cutting-edge technology and verification techniques. Team player with strong problem-solving skills to contribute effectively to projects and teams. Considers unique and unconventional solutions to deliver exceptional results.
Overview
15
15
years of professional experience
Work History
GPU Design verification ENGINEER
INTEL CORPORATION
11.2021 - Current
- Working in the model integration team and responsible for functional bring-up of pre-silicon Verification Graphics IP environment for Client, Server and Compute chips.
- Wrote the python-based tool to create emulation friendly verification components and their seamless integration at IP validation environment using Machine Readable based Specifications (JSON format) and Template tool kit.
- Lead a team of around 10 junior engineers to integrate the tool for around 600 validation components across 60 sub-IP verification environments resulting in efficient functional bring-up of tracker and checker model at GFX IP. The bring up time is reduced to 2 days from 1 month of effort.
STAFF DESIGN ENGINEER
MICRON TECHNOLOGY
08.2020 - 11.2021
- Worked on owning the white-box erase behavior model for 3D NAND based RTL design & firmware.
- Worked on bringing up the RAL (Register Layer) for NAND verification environment from scratch.
ASIC Digital DESIGN ENGINEER, SENIOR II
SYNOPSYS
12.2019 - 08.2020
- Worked on verifying LPDDR5 PHY IP involving DFI protocol on the DDR controller and JEDEC protocol on the DRAM.
- Worked on verifying clock gating in the LPDDR PHY design using assertion based checkers & coverage.
- Worked on bringing up the DDR Synopsys controller IP driver in the unit verification sub-system.
Senior VERIFICATION ENGINEER
NVIDIA
07.2017 - 12.2019
- Worked on verifying arbiter unit in memory subsystem interacting with graphics clients, MMU and caches.
- Took the initiative to bring up UVM environment from scratch and successfully build a hybrid C++ & UVM environment. UVM environment is gradually adopted by various memory subsystem unit environments.
- Successfully verified the dynamic complex feature in the unit involving writing the new UVM sequences, new UVM multiple scoreboards, UVM black box coverage and regressions.
- Developed scalable and parameterizable UVM components for clients, their constraints and checking.
- Wrote the Perl script to ease and automate the addition of new interface in various UVM components.
- Wrote the hang detector UVCs, trackers and watchdog timer UVC for ease of debug.
STAFF VERIFICATION ENGINEER
SAMSUNG RESEARCH AMERICA
10.2016 - 06.2017
- Worked on verifying the network-on chip (NOC) based multilevel cache memory sub-system using UVM.
- Took responsibility to create a top-level configuration object for UVM components for better test control.
- Developed a new generic scalable UVM scoreboard to be used at various validation environments.
- Took initiative to write generic UVCs instantiated in virtual sequencers & for transaction level coverage.
- Wrote new virtual sequences and debugged failures for the feature bring up.
GRAPHICS HARDWARE ENGINEER
INTEL CORPORATION
08.2011 - 10.2016
- Worked as pre-silicon verification Engineer for Graphics interface team at various unit level and full chip validation environments for 5 projects with multiple stepping.
- Quickly ramped up on MESI protocol based, emulation friendly DPI C/C++ & Verilog BFM modelling CPU and GPU interactions and made critical enhancements for cache coherency and supported unit level, full chip simulation, emulation & driver functional and performance validation environments.
- Performed unit level validation for MESI and clock crossing FIFO based design. Wrote new tests, ran validation cycles, debug failures and maintained System Verilog scoreboard for new features.
- Took ownership and verified the Graphics cache coherency bring up both at unit level and full chip validation environment.
- Worked on the validation of PCIe protocol-based design and ran regression, debug failures, wrote new test cases and JAVA based scoreboard from scratch.
- As a part of Graphics interface team, set up a new cross unit validation environment for testing out the interactions between various units. Converted all the unit level components into scalable, parameterized components to be integrated at inter unit level. Eventually, team grew to four people and lead the validation effort to find around 50 cross unit interaction bugs.
IC DESIGN ENGINEER
LSI CORPORATION
10.2010 - 08.2011
- Worked as a Verification Engineer for the PCIe team.
- Wrote basic PCIe UVM sequences (Memory read/write, IO read/write and configuration read/write & error injection sequences) as a part of integration of Synopsis UVM based PCIe trans-receiver VIP in unit level validation environment.
- Wrote UVM configuration object address manager to allocate random & unique addresses to clients attached to PCIe.
EMBEDDED SYSTEMS ENGINNER
SYN-TECH SYSTEMS INC.
02.2010 - 10.2010
- Debugged and fixed various bugs to test software code for Syn-Tech's produce support effort relative to customer's use of FUELMASTER accounting system using C language.
Education
MS - ELECTRICAL & COMPUTER ENGINEERING
UNIVERSITY OF FLORIDA
GAINESVILLE, FL12.2009
B. TECH - Electronics & COMMUNICATION ENGINEERING
NIT KURUKSHETRA
KURUKSHETRA, HR05.2007
Skills
- System Verilog/ UVM
- Coverage
- SVA (System Verilog Assertions)
- Test Plans
- VCS Verdi & DVE
- DPI C/C/Verilog BFMs
- Perl/ Python
- Scoreboards/ Checkers
- Drivers/ Sequencers
- Virtual sequencers/ sequencers
- Computer Architecture
- Cache Coherency
- Network on-chip protocol
- Machine Readable Specifications based Automation
Accomplishments
- Documented and created a python based tool using machine readable specs at Intel·
- Supervised a team of 10 team members and collaborated with 60 sub-IPs to successfully deploy the tool.
- Successfully developed UVM environment from starch single handedly for the unit level verification environment at NVIDIA.
- Supervised a highly efficient team of 3 people to build a sub-IP verification environment from scratch consisting of multiple sub-IPs. Achieved 50 cross sub-IPs bugs before validation at IP.
- Intel VPG HWE Department Recognition Award (DRA) Q2, 2015 for initiative in development of the System Verilog scalable validation environment consisting of all the Graphics interface DUTs.
- Intel VPG HWE Department Recognition Award (DRA) Q2, 2012 in recognition of efforts in developing the System Verilog validation environment for memory interface DUT with high quality and within schedule.
Timeline
GPU Design verification ENGINEER
INTEL CORPORATION
11.2021 - Current
STAFF DESIGN ENGINEER
MICRON TECHNOLOGY
08.2020 - 11.2021
ASIC Digital DESIGN ENGINEER, SENIOR II
SYNOPSYS
12.2019 - 08.2020
Senior VERIFICATION ENGINEER
NVIDIA
07.2017 - 12.2019
STAFF VERIFICATION ENGINEER
SAMSUNG RESEARCH AMERICA
10.2016 - 06.2017
GRAPHICS HARDWARE ENGINEER
INTEL CORPORATION
08.2011 - 10.2016
IC DESIGN ENGINEER
LSI CORPORATION
10.2010 - 08.2011
EMBEDDED SYSTEMS ENGINNER
SYN-TECH SYSTEMS INC.
02.2010 - 10.2010
MS - ELECTRICAL & COMPUTER ENGINEERING
UNIVERSITY OF FLORIDA
B. TECH - Electronics & COMMUNICATION ENGINEERING
NIT KURUKSHETRA
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